arch-gcn3, gpu-compute: Fix issue when reading const operands

Currently, when an instruction has an operand that reads a const
value, it goes thru the same readMiscReg() api call as other
misc registers (real HW registers, not constant values). There
is an issue, however, when casting from the const values (which are
32b) to higher precision values, like 64b.

This change creates a separate, templated function call to the GPU's
ISA state that will return the correct type.

Change-Id: I41965ebeeed20bb70e919fce5ad94d957b3af802
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29927
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/gcn3/gpu_isa.hh

@@ -37,6 +37,7 @@
 #define __ARCH_GCN3_GPU_ISA_HH__
 
 #include <array>
+#include <type_traits>
 
 #include "arch/gcn3/registers.hh"
 #include "gpu-compute/dispatcher.hh"
@@ -52,6 +53,24 @@ namespace Gcn3ISA
       public:
         GPUISA(Wavefront &wf);
 
+        template<typename T> T
+        readConstVal(int opIdx) const
+        {
+            panic_if(!std::is_integral<T>::value, "Constant values must "
+                     "be an integer.\n");
+            T val(0);
+
+            if (isPosConstVal(opIdx)) {
+                val = (T)readPosConstReg(opIdx);
+            }
+
+            if (isNegConstVal(opIdx)) {
+                val = (T)readNegConstReg(opIdx);
+            }
+
+            return val;
+        }
+
         ScalarRegU32 readMiscReg(int opIdx) const;
         void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
         bool hasScalarUnit() const { return true; }
@@ -63,10 +82,9 @@ namespace Gcn3ISA
             return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
         }
 
-        ScalarRegU32 readNegConstReg(int opIdx) const
+        ScalarRegI32 readNegConstReg(int opIdx) const
         {
-            return *((ScalarRegU32*)
-                &negConstRegs[opIdx - REG_INT_CONST_NEG_MIN]);
+            return negConstRegs[opIdx - REG_INT_CONST_NEG_MIN];
         }
 
         static const std::array<const ScalarRegU32, NumPosConstRegs>

src/arch/gcn3/isa.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017 Advanced Micro Devices, Inc.
+ * Copyright (c) 2016-2018 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * For use for simulation and test purposes only
@@ -49,14 +49,6 @@ namespace Gcn3ISA
     ScalarRegU32
     GPUISA::readMiscReg(int opIdx) const
     {
-        if (opIdx >= REG_INT_CONST_POS_MIN && opIdx <= REG_INT_CONST_POS_MAX) {
-            return readPosConstReg(opIdx);
-        }
-
-        if (opIdx >= REG_INT_CONST_NEG_MIN && opIdx <= REG_INT_CONST_NEG_MAX) {
-            return readNegConstReg(opIdx);
-        }
-
         switch (opIdx) {
           case REG_M0:
             return m0;

src/arch/gcn3/operand.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 Advanced Micro Devices, Inc.
+ * Copyright (c) 2017-2018 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * For use for simulation and test purposes only
@@ -583,10 +583,15 @@ namespace Gcn3ISA
               default:
                 {
                     assert(sizeof(DataType) <= sizeof(srfData));
-                    DataType misc_val
-                        = (DataType)_gpuDynInst->readMiscReg(_opIdx);
+                    DataType misc_val(0);
+                    if (isConstVal(_opIdx)) {
+                        misc_val = (DataType)_gpuDynInst
+                            ->readConstVal<DataType>(_opIdx);
+                    } else {
+                        misc_val = (DataType)_gpuDynInst->readMiscReg(_opIdx);
+                    }
                     std::memcpy((void*)srfData.data(), (void*)&misc_val,
-                        sizeof(DataType));
+                                sizeof(DataType));
                 }
             }
         }

src/arch/gcn3/registers.cc

@@ -162,6 +162,31 @@ namespace Gcn3ISA
         return regIdx;
     }
 
+    bool
+    isPosConstVal(int opIdx)
+    {
+        bool is_pos_const_val = (opIdx >= REG_INT_CONST_POS_MIN
+            && opIdx <= REG_INT_CONST_POS_MAX);
+
+        return is_pos_const_val;
+    }
+
+    bool
+    isNegConstVal(int opIdx)
+    {
+        bool is_neg_const_val = (opIdx >= REG_INT_CONST_NEG_MIN
+            && opIdx <= REG_INT_CONST_NEG_MAX);
+
+        return is_neg_const_val;
+    }
+
+    bool
+    isConstVal(int opIdx)
+    {
+        bool is_const_val = isPosConstVal(opIdx) || isNegConstVal(opIdx);
+        return is_const_val;
+    }
+
     bool
     isLiteral(int opIdx)
     {

src/arch/gcn3/registers.hh

@@ -238,6 +238,9 @@ namespace Gcn3ISA
 
     std::string opSelectorToRegSym(int opIdx, int numRegs=0);
     int opSelectorToRegIdx(int opIdx, int numScalarRegs);
+    bool isPosConstVal(int opIdx);
+    bool isNegConstVal(int opIdx);
+    bool isConstVal(int opIdx);
     bool isLiteral(int opIdx);
     bool isScalarReg(int opIdx);
     bool isVectorReg(int opIdx);

src/gpu-compute/gpu_exec_context.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 Advanced Micro Devices, Inc.
+ * Copyright (c) 2015-2018 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * For use for simulation and test purposes only
@@ -48,6 +48,12 @@ class GPUExecContext
     Wavefront* wavefront();
     ComputeUnit* computeUnit();
 
+    template<typename T> T
+    readConstVal(int opIdx) const
+    {
+        return gpuISA->readConstVal<T>(opIdx);
+    }
+
     RegVal readMiscReg(int opIdx) const;
     void writeMiscReg(int opIdx, RegVal operandVal);