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gem5/src/arch/riscv
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Gabe Black 93a01dba47 arch: Use VPtr for uname. 
Change-Id: Ia4b6c9135f16e6c68bbcf3a9c15ba7433a0a6682
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29403
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2020-08-05 23:52:25 +00:00
..
bare_metal
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
2020-06-09 23:37:29 +00:00
insts
arch-riscv: Fix disassembling of float register instructions
2020-08-01 02:14:37 +00:00
isa
arch-riscv: let FPU instructions fault if status.FS = off.
2020-04-29 11:41:55 +00:00
linux
arch: Use VPtr for uname.
2020-08-05 23:52:25 +00:00
decoder.cc
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
decoder.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
faults.cc
arch-riscv: fixed read of {M,S,U}TVEC.
2020-04-29 11:41:55 +00:00
faults.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
fs_workload.hh
arch,sim,kern,dev,cpu: Create a Workload SimObject.
2020-04-22 00:22:28 +00:00
idle_event.cc
arch,cpu,sim: Eliminate the now empty kernel statistics classes.
2020-06-17 19:54:41 +00:00
idle_event.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
interrupts.cc
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
interrupts.hh
arch,cpu: Change setCPU to setThreadContext in Interrupts.
2020-06-11 23:42:54 +00:00
isa_traits.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
isa.cc
arch,cpu: Add a setThreadContext method to the ISA class.
2020-06-12 05:41:41 +00:00
isa.hh
arch,cpu: Add a setThreadContext method to the ISA class.
2020-06-12 05:41:41 +00:00
locked_mem.cc
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
locked_mem.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
microcode_rom.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
pagetable_walker.cc
arch-riscv,tests: small update to make gem5.fast compile
2020-05-11 23:33:15 +00:00
pagetable_walker.hh
arch-riscv: be prepared for CSR changes during PT walk.
2020-05-02 05:04:50 +00:00
pagetable.cc
arch-riscv: added TLB and page table walker.
2020-04-29 11:41:55 +00:00
pagetable.hh
arch-riscv: added TLB and page table walker.
2020-04-29 11:41:55 +00:00
pra_constants.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
process.cc
arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.
2020-06-09 23:37:29 +00:00
process.hh
base,arch,sim,cpu: Move object file loader components into a namespace.
2020-04-22 06:08:54 +00:00
pseudo_inst.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
registers.hh
arch-riscv: respect IALIGN, influenced by toggling 'c' extension.
2020-04-29 11:41:55 +00:00
remote_gdb.cc
arch-riscv: implement RemoteGDB::acc for FS mode.
2020-04-29 11:41:55 +00:00
remote_gdb.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvFsWorkload.py
arch,sim,kern,dev,cpu: Create a Workload SimObject.
2020-04-22 00:22:28 +00:00
RiscvInterrupts.py
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvISA.py
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvTLB.py
arch-riscv: added TLB and page table walker.
2020-04-29 11:41:55 +00:00
SConscript
arch,cpu: Consolidate most of the StackTrace classes into a base class.
2020-07-11 00:24:38 +00:00
SConsopts
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
stacktrace.hh
arch,cpu: Consolidate most of the StackTrace classes into a base class.
2020-07-11 00:24:38 +00:00
tlb.cc
arch-riscv: be prepared for CSR changes during PT walk.
2020-05-02 05:04:50 +00:00
tlb.hh
arch-riscv: be prepared for CSR changes during PT walk.
2020-05-02 05:04:50 +00:00
types.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
utility.hh
arch-riscv: added support for pseudo instructions.
2020-03-26 08:28:43 +00:00