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arch-riscv: Fix disassembling of float register instructions

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In disassembling of float register instructions, Gem5 always gives 2
source registers rs1 and rs2. However, this is not correct for Mul-Add
instructions which have three rs1, rs2, and rs3, and for Move, Convert
instructions which have only rs1.

For example: (Gem5  output  vs Expected)
- fmadd.d fa0,fa0,fa4 vs  fmadd.d fa0,fa0,fa4,fa5
- fcvt.d.l fa4,a6,zero  vs  fcvt.d.l fa4,a6

This patch fixes the problem.

Change-Id: I02d840eab602ac4a9782911b3cdff2935dfe5e68
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32054
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ian Jiang
2020-07-31 16:00:05 +08:00
parent 9f033ee6c8
commit ae75e7fc45
1 changed files with 5 additions and 2 deletions
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7
src/arch/riscv/insts/standard.cc
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@@ -47,8 +47,11 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
registerName(_srcRegIdx[0]) << ", " <<
registerName(_srcRegIdx[1]);
registerName(_srcRegIdx[0]);
if (_srcRegIdx[1].index() != 0)
ss << ", " << registerName(_srcRegIdx[1]);
if (_srcRegIdx[2].index() != 0)
ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}