diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index bb621ae7a6..e6c2b67aed 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -47,8 +47,11 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
     stringstream ss;
     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-        registerName(_srcRegIdx[0]) << ", " <<
-        registerName(_srcRegIdx[1]);
+        registerName(_srcRegIdx[0]);
+    if (_srcRegIdx[1].index() != 0)
+        ss << ", " << registerName(_srcRegIdx[1]);
+    if (_srcRegIdx[2].index() != 0)
+        ss << ", " << registerName(_srcRegIdx[2]);
     return ss.str();
 }