Giacomo Travaglini b4f9e0a02f arch, cpu: Add a takeOverFrom method for switching ISAs ...

This will be used by architectures to handle the m5.switchCpus at the
ISA level since some ISA specific fields might need to be aware of the
TC change.

Change-Id: If8d50c5c80bc3458d5f1d14cf93ae107314c98cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27712
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-04-15 07:34:09 +00:00

..

arm

arch-arm: Remove unnecessary haveGICv3CPUInterface

2020-04-15 07:34:09 +00:00

generic

arch, cpu: Add a takeOverFrom method for switching ISAs

2020-04-15 07:34:09 +00:00

hsail

arch,cpu,gpu-compute,mem: Remove asid from Request objects.

2020-03-07 00:40:41 +00:00

mips

sim-se: Switch to new MemState API

2020-03-25 19:18:15 +00:00

null

arch: Delete authors lists from the null arch files.

2020-02-18 03:35:12 +00:00

power

sim-se: Switch to new MemState API

2020-03-25 19:18:15 +00:00

riscv

riscv: Fix RISCV builds by updating its use of pseudoInst().

2020-03-27 21:14:51 +00:00

sparc

sim-se: Switch to new MemState API

2020-03-25 19:18:15 +00:00

x86

arch-x86: Do not fixup faults in TLB

2020-04-09 17:03:38 +00:00

isa_parser.py

arch: list.sort() sorting by key only in python3

2020-03-13 14:24:07 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch: Eliminate vtophys and its switching header file.

2020-03-19 01:38:01 +00:00