arch-arm: Remove unnecessary haveGICv3CPUInterface
This is not needed since the ISA class could just check if the gicv3CpuInterface ptr is different than nullptr Change-Id: I6d562a5d9ff2568774b6958f03f04d878266ca8f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27711 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -60,7 +60,7 @@ namespace ArmISA
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ISA::ISA(Params *p) : BaseISA(p), system(NULL),
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_decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
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pmu(p->pmu), haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop),
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pmu(p->pmu), impdefAsNop(p->impdef_nop),
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afterStartup(false)
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{
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miscRegs[MISCREG_SCTLR_RST] = 0;
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@@ -428,7 +428,6 @@ ISA::startup(ThreadContext *tc)
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if (system) {
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Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
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if (gicv3) {
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haveGICv3CPUInterface = true;
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gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
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gicv3CpuInterface->setISA(this);
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gicv3CpuInterface->setThreadContext(tc);
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@@ -744,7 +743,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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(haveVirtualization ? 0x0000000000000200 : 0) | // EL2
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(haveSecurity ? 0x0000000000002000 : 0) | // EL3
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(haveSVE ? 0x0000000100000000 : 0) | // SVE
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(haveGICv3CPUInterface ? 0x0000000001000000 : 0);
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(gicv3CpuInterface ? 0x0000000001000000 : 0);
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case MISCREG_ID_AA64PFR1_EL1:
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return 0; // bits [63:0] RES0 (reserved for future use)
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@@ -91,7 +91,6 @@ namespace ArmISA
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bool haveVirtualization;
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bool haveCrypto;
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bool haveLargeAsid64;
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bool haveGICv3CPUInterface;
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uint8_t physAddrRange;
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bool haveSVE;
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bool haveLSE;
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@@ -746,14 +745,14 @@ namespace ArmISA
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Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
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/** Getter for haveGICv3CPUInterface */
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/** Returns true if the ISA has a GICv3 cpu interface */
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bool haveGICv3CpuIfc() const
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{
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// haveGICv3CPUInterface is initialized at startup time, hence
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// gicv3CpuInterface is initialized at startup time, hence
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// trying to read its value before the startup stage will lead
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// to an error
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assert(afterStartup);
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return haveGICv3CPUInterface;
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return gicv3CpuInterface != nullptr;
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}
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Enums::VecRegRenameMode
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