Giacomo Travaglini acd148a76c arch-arm: Set CM bit in DataAbort ...

The CM bit in a DataAbort ISS indicates whether the Data Abort came from
a cache maintenance or address translation instruction.

Change-Id: I8888520446550581c8dd0507a8989935db7047be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-10-03 09:05:19 +00:00

..

arch

arch-arm: Set CM bit in DataAbort

2019-10-03 09:05:19 +00:00

base

stats: Add a preDumpStats() callback to Stats::Group

2019-09-26 10:05:03 +00:00

cpu

cpu: Make use of DRAMCtrl::AddrMap in the traffic generators

2019-09-30 20:36:30 +00:00

dev

dev-arm: Improve fault message on SMMUv3 translation fault

2019-10-02 15:55:06 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

gpu-compute: Fix overriden errors

2019-09-20 22:42:31 +00:00

kern

kern: Replace an explicitly instantiated port proxy with one from the tc.

2019-05-30 14:20:03 +00:00

learning_gem5

dev: Scrub out some lingering uses of MemObject.

2019-09-09 01:54:36 +00:00

mem

mem-cache: Fix invalid whenReady

2019-10-01 06:19:38 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

misc: Added line wrapping functionality for Sim-Object desc

2019-09-30 19:50:26 +00:00

sim

sim: Mark System::getThreadContext method as const

2019-10-02 15:56:42 +00:00

systemc

systemc: Make TLM port wrappers for tlm_base_(target|initiator)_socket.

2019-09-17 19:07:59 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00