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arch-arm: Set CM bit in DataAbort

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The CM bit in a DataAbort ISS indicates whether the Data Abort came from
a cache maintenance or address translation instruction.

Change-Id: I8888520446550581c8dd0507a8989935db7047be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-09-12 10:23:16 +01:00
parent 79c9ae0306
commit acd148a76c
2 changed files with 9 additions and 1 deletions
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6
src/arch/arm/faults.cc
View File

@@ -1369,6 +1369,9 @@ DataAbort::iss() const
// Add on the data abort specific fields to the generic abort ISS value
val = AbortFault<DataAbort>::iss();
val |= cm << 8;
// ISS is valid if not caused by a stage 1 page table walk, and when taken
// to AArch64 only when directed to EL2
if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
@@ -1412,6 +1415,9 @@ DataAbort::annotate(AnnotationIDs id, uint64_t val)
isv = true;
ar = val;
break;
case CM:
cm = val;
break;
// Just ignore unknown ID's
default:
break;

4
src/arch/arm/faults.hh
View File

@@ -136,6 +136,7 @@ class ArmFault : public FaultBase
SAS, // DataAbort: Syndrome Access Size
SSE, // DataAbort: Syndrome Sign Extend
SRT, // DataAbort: Syndrome Register Transfer
CM, // DataAbort: Cache Maintenance/Address Translation Op
// AArch64 only
SF, // DataAbort: width of the accessed register is SixtyFour
@@ -482,6 +483,7 @@ class DataAbort : public AbortFault<DataAbort>
uint8_t sas;
uint8_t sse;
uint8_t srt;
uint8_t cm;
// AArch64 only
bool sf;
@@ -491,7 +493,7 @@ class DataAbort : public AbortFault<DataAbort>
bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
_tranMethod),
isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
{}
ExceptionClass ec(ThreadContext *tc) const override;