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a8d5dd1c136529e9605066368877d3b8e24dcdba
gem5/src/mem
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Nikos Nikoleris a8d5dd1c13 mem-cache: Fix MSHR handling of cache clean requests 
Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.

Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-04-10 09:05:02 +00:00
..
cache
mem-cache: Fix MSHR handling of cache clean requests
2019-04-10 09:05:02 +00:00
probes
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
protocol
mem-ruby: Fixing MESI Three Level
2019-02-12 05:51:07 +00:00
qos
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
ruby
misc: missing override specifier
2019-03-23 00:05:33 +00:00
slicc
python: Stop using basestring to test for strings
2019-02-25 14:25:24 +00:00
abstract_mem.cc
mem: Compile tracePacket only when TRACING_ON is defined
2018-12-07 13:28:19 +00:00
abstract_mem.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
AbstractMemory.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
addr_mapper.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
addr_mapper.hh
misc: missing override specifier
2019-03-23 00:05:33 +00:00
AddrMapper.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
backdoor.hh
mem: Add a MemBackdoor type to track memory backdoors.
2019-04-06 00:52:15 +00:00
bridge.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
bridge.hh
misc: missing override specifier
2019-03-23 00:05:33 +00:00
Bridge.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
coherent_xbar.cc
mem: Clean up the xbars a little.
2019-03-26 18:17:09 +00:00
coherent_xbar.hh
mem: Clean up the xbars a little.
2019-03-26 18:17:09 +00:00
comm_monitor.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
comm_monitor.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
CommMonitor.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
dram_ctrl.cc
mem: Reverse order of write/read mem queue check
2019-04-05 17:36:37 +00:00
dram_ctrl.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
DRAMCtrl.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
drampower.cc
mem: Remove unused 'using namespace'
2018-04-06 08:38:06 +00:00
drampower.hh
mem: Fix search-replace issues in DRAMPower wrapper license
2015-11-25 13:52:56 -05:00
dramsim2_wrapper.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
dramsim2_wrapper.hh
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
dramsim2.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
dramsim2.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
DRAMSim2.py
mem: Add a wrapped DRAMSim2 memory controller
2014-02-18 05:50:53 -05:00
external_master.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
external_master.hh
misc: missing override specifier
2019-03-23 00:05:33 +00:00
external_slave.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
external_slave.hh
misc: missing override specifier
2019-03-23 00:05:33 +00:00
ExternalMaster.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
ExternalSlave.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
fs_translating_port_proxy.cc
mem: Remove unused 'using namespace'
2018-04-06 08:38:06 +00:00
fs_translating_port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
hmc_controller.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
hmc_controller.hh
mem: Standardize mem folder header guards
2018-02-06 10:26:27 +00:00
HMCController.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
mem_checker_monitor.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
mem_checker_monitor.hh
misc: missing override specifier
2019-03-23 00:05:33 +00:00
mem_checker.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
mem_checker.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
mem_delay.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
mem_delay.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
mem_master.hh
sim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-27 16:00:28 +00:00
mem_object.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
mem_object.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
MemChecker.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
MemDelay.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
MemObject.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
mport.cc
MEM: Separate snoops and normal memory requests/responses
2012-04-14 05:45:07 -04:00
mport.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
multi_level_page_table.hh
x86, mem: Rewrite the multilevel page table class.
2018-01-23 20:14:48 +00:00
noncoherent_xbar.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
noncoherent_xbar.hh
mem: Clean up the xbars a little.
2019-03-26 18:17:09 +00:00
packet_access.hh
null: Stop specifying an endianness in isa_traits.hh.
2018-10-18 07:48:10 +00:00
packet_queue.cc
mem: Allow inserts in the begining of a packet queue
2019-01-17 11:09:41 +00:00
packet_queue.hh
mem: Determine if a packet queue forces ordering at construction
2019-01-17 11:09:41 +00:00
packet.cc
mem-cache: Copy over flags to forwarded response
2019-02-26 11:17:58 +00:00
packet.hh
mem-cache: Copy over flags to forwarded response
2019-02-26 11:17:58 +00:00
page_table.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
page_table.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
physical.cc
mem: Use address range to find the right physical address
2018-06-19 14:24:25 +00:00
physical.hh
mem: Use the caching in the AddrRangeMap class in PhysicalMemory
2018-06-19 14:24:25 +00:00
port_proxy.cc
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
port.cc
mem: Move bind() and unbind() into the Port class.
2019-03-19 10:21:46 +00:00
port.hh
mem: Move bind() and unbind() into the Port class.
2019-03-19 10:21:46 +00:00
qport.hh
mem: Determine if a packet queue forces ordering at construction
2019-01-17 11:09:41 +00:00
request.hh
arch-arm: We add PRFM PST instruction for arm
2018-10-26 12:47:46 +00:00
SConscript
mem: Add a QoS-aware Memory Controller type
2018-09-07 13:16:20 +00:00
se_translating_port_proxy.cc
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
se_translating_port_proxy.hh
mem: Refactor port proxies to support secure accesses
2018-02-19 14:24:46 +00:00
serial_link.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
serial_link.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
SerialLink.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
simple_mem.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
simple_mem.hh
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
SimpleMemory.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
snoop_filter.cc
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
snoop_filter.hh
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
stack_dist_calc.cc
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
stack_dist_calc.hh
mem: Redesign the stack distance calculator as a probe
2015-08-04 10:29:13 +01:00
tport.cc
mem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-07-23 11:57:50 +00:00
tport.hh
mem: Unify delayed packet deletion
2015-11-06 03:26:21 -05:00
xbar.cc
mem: Clean up the xbars a little.
2019-03-26 18:17:09 +00:00
xbar.hh
mem: Deleting this init() method was accidentally dropped during rebase.
2019-03-26 18:31:59 +00:00
XBar.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00