Gabe Black a119a96324 cpu, arch: Replace the CCReg type with RegVal. ...

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

2019-02-01 01:22:19 +00:00

..

bare_metal

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

insts

arch-riscv: Add support for trap value register

2018-07-28 18:48:30 +00:00

isa

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

linux

sim-se: add syscalls related to polling

2019-01-22 02:05:48 +00:00

decoder.cc

riscv,x86: Stop using the arch Nop machine instruction unnecessarily.

2017-12-23 03:36:45 +00:00

decoder.hh

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

2018-03-27 10:57:54 +00:00

faults.cc

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

faults.hh

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

idle_event.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

idle_event.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

interrupts.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

interrupts.hh

arch-riscv: Add interrupt handling

2019-01-16 00:20:34 +00:00

isa_traits.hh

alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

2018-01-10 12:19:54 +00:00

isa.cc

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

isa.hh

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

kernel_stats.hh

stats: Get rid of some kernel stats related cruft.

2017-09-11 04:58:38 +00:00

locked_mem.cc

riscv: fix Linux problems with LR and SC ops

2017-04-05 20:21:59 +00:00

locked_mem.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

microcode_rom.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

mmapped_ipr.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

pagetable.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

pagetable.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

pra_constants.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

process.cc

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

process.hh

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

pseudo_inst.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

registers.hh

cpu, arch: Replace the CCReg type with RegVal.

2019-02-01 01:22:19 +00:00

remote_gdb.cc

arch: cpu: Rename *FloatRegBits* to *FloatReg*.

2019-01-31 11:02:05 +00:00

remote_gdb.hh

riscv: Get rid of some ISA specific register types.

2019-01-31 11:03:21 +00:00

RiscvInterrupts.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

RiscvISA.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

RiscvSystem.py

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

RiscvTLB.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

SConscript

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

SConsopts

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

stacktrace.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

stacktrace.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

system.cc

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

system.hh

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

tlb.cc

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

tlb.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

types.hh

arch-riscv: Add support for compressed extension RV64C

2017-07-11 03:45:14 +00:00

utility.cc

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

utility.hh

arch-riscv: enable rudimentary fs simulation

2018-07-09 11:17:11 +00:00

vtophys.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00