Roger Chang 9ce8c9b81c arch-riscv: Refactor template JumpConstructor ...

Add COPCODE == 4 condition to ensure the available instruction is either c_jr or c_jalr and the flag IsReturn should set for instruction c_jalr if RC1 == t0

Change-Id: I1b39a6c1dc52c8035f16cc64a1b4c494b14879c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66811
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>

2022-12-23 00:28:11 +00:00

..

arch

arch-riscv: Refactor template JumpConstructor

2022-12-23 00:28:11 +00:00

base

base: Fix signature of SatCounter::saturate()

2022-12-19 01:58:31 +00:00

cpu

python: Fix multiline quotes in a single line

2022-11-29 23:44:38 +00:00

dev

dev: Fix -Wunused-variable in structured binding

2022-12-22 08:07:51 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Fix ABI init for DispatchId

2022-12-16 18:16:18 +00:00

kern

arch-x86,sim-se: Add clone3 syscall

2022-10-27 23:57:43 +00:00

learning_gem5

python: Fix multiline quotes in a single line

2022-11-29 23:44:38 +00:00

mem

mem: Implement and use the recvMemBackdoorReq func.

2022-12-13 00:20:13 +00:00

proto

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

python

python: Remove 'scheduleTickExit' in favor of 'exitSimLoop'

2022-12-06 18:04:46 +00:00

sim

dev: Implement a "Signal" port which has a templated State type.

2022-12-16 07:19:05 +00:00

sst

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

systemc

systemc: Enable DMI in the non-blocking/timing mode bridge.

2022-12-07 12:23:35 +00:00

Doxyfile

misc: Stop excluding code when building the NULL ISA.

2022-08-20 07:30:07 +00:00

SConscript

scons: fix protobuf action for imports

2022-10-15 14:22:03 +00:00