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9883fb6b58f0e1a7f6d66f52eb29e534cc5f652f
gem5/src/cpu
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Brandon Potter 9883fb6b58 scons,ruby: do not generate unnecessary files 
Do not generate garnet tester file or Ruby debug headers without a Ruby
protocol (i.e. PROTOCOL=None). It makes no sense to include these files
into the build when there will be no protocol to utilize them.

Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104
Reviewed-on: https://gem5-review.googlesource.com/8381
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17 17:21:02 +00:00
..
checker
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
kvm
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
minor
cpu-minor: Remove redundant thread startup call
2018-06-14 12:54:47 +00:00
nocpu
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
o3
cpu: Removed unnecessary file reg_class_impl.hh
2018-08-10 23:41:23 +00:00
pred
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
simple
cpu: Prevent suspended TimingSimple CPUs from fetching next instructions
2018-06-14 22:42:16 +00:00
testers
scons,ruby: do not generate unnecessary files
2018-08-17 17:21:02 +00:00
trace
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
activity.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
activity.hh
cpu: Useful getters for ActivityRecorder
2014-05-09 18:58:48 -04:00
base_dyn_inst_impl.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00
base_dyn_inst.hh
cpu: add a new instruction type 'Atomic'
2018-06-14 22:41:30 +00:00
base.cc
cpu: Fix bug introduced by RequestPtr type change
2018-06-21 12:09:19 +00:00
base.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
BaseCPU.py
scons: Switch from the print statement to the print function.
2018-03-06 23:39:01 +00:00
CheckerCPU.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
cpuevent.cc
…
cpuevent.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
CPUTracers.py
cpu: Put all CPU instruction tracers in a single file
2015-01-25 07:22:17 -05:00
decode_cache.hh
arch: cpu: Make the ExtMachInst type a template argument in InstMap.
2018-03-27 10:57:54 +00:00
dummy_checker.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
dummy_checker.hh
cpu: Add header files for checker CPUs
2012-11-02 11:32:01 -05:00
DummyChecker.py
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
2013-02-15 17:40:08 -05:00
exec_context.cc
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
exec_context.hh
cpu, power: Get rid of the remnants of the EA computation insts.
2018-01-09 03:02:26 +00:00
exetrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
exetrace.hh
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
func_unit.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
func_unit.hh
cpu: Fix issue identified by UBSan
2015-07-30 03:41:22 -04:00
FuncUnit.py
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
2016-10-15 14:58:45 -05:00
inst_pb_trace.cc
cpu: Stop extracting inst_flags from the machInst.
2018-03-27 10:57:36 +00:00
inst_pb_trace.hh
cpu: Use the new asBytes function in the protobuf inst tracer.
2018-03-26 22:34:03 +00:00
inst_res.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
inst_seq.hh
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
InstPBTrace.py
cpu: add support for outputing a protobuf formatted CPU trace
2015-02-16 03:32:38 -05:00
inteltrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
inteltrace.hh
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
intr_control_noisa.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
intr_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
intr_control.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
IntrControl.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
nativetrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
nativetrace.hh
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
op_class.hh
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
2016-10-15 14:58:45 -05:00
pc_event.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
pc_event.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
profile.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
profile.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
quiesce_event.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
quiesce_event.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
reg_class.cc
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
reg_class.hh
cpu: Add hash functionality for RegId class
2018-08-10 23:41:23 +00:00
SConscript
sim: add ExecMacro to Exec* compound debug flags
2015-10-06 17:26:50 -07:00
simple_thread.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
simple_thread.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
smt.hh
includes: fix up code after sorting
2011-04-15 10:44:14 -07:00
static_inst_fwd.hh
cpu: Don't forward declare RefCountingPtr
2014-08-13 06:57:26 -04:00
static_inst.cc
cpu: Add a pointer to a generic Nop StaticInst.
2017-12-22 00:27:20 +00:00
static_inst.hh
cpu: Removed unnecessary file reg_class_impl.hh
2018-08-10 23:41:23 +00:00
StaticInstFlags.py
cpu: add a new instruction type 'Atomic'
2018-06-14 22:41:30 +00:00
thread_context.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
thread_context.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
thread_state.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
thread_state.hh
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
timebuf.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
timing_expr.cc
cpu: Simplify the rename interface and use RegId
2017-07-05 14:43:49 +00:00
timing_expr.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
TimingExpr.py
cpu: `Minor' in-order CPU model
2014-07-23 16:09:04 -05:00
translation.hh
misc: Using smart pointers for memory Requests
2018-06-11 16:55:30 +00:00