Giacomo Travaglini 96e72d6ecd arch-arm: Use VecElem instead of FloatReg for FP instruction ...

SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in
AArch64 mode. The usage of two different register pools breaks
interprocessing between A32 and A64.  This patch is changing definition
of arm operands so that they are backed by VecElems in A32, which are
mapped to the same storage as A64 VecRegs.

Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217
Reviewed-on: https://gem5-review.googlesource.com/c/15603
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-01-25 12:55:27 +00:00

..

alpha

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

arm

arch-arm: Use VecElem instead of FloatReg for FP instruction

2019-01-25 12:55:27 +00:00

generic

cpu, arch, arch-arm: Wire unused VecElem code in the O3 model

2019-01-25 12:55:27 +00:00

hsail

hsail: Remove the MiscReg type.

2019-01-24 23:44:34 +00:00

mips

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

null

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

power

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

riscv

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

sparc

sparc: Get rid of some register type definitions.

2019-01-22 21:16:10 +00:00

x86

base: arch: Get rid of the now unused FloatRegVal type.

2019-01-24 23:42:22 +00:00

isa_parser.py

arch: Fix VecElem Operand generation in ISA parser

2019-01-25 12:55:27 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "arch/tlb.hh" switching header.

2018-01-23 20:39:24 +00:00