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sparc: Get rid of some register type definitions.

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These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.

Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44
Reviewed-on: https://gem5-review.googlesource.com/c/13627
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2018-10-18 17:50:42 -07:00
parent 230b892fa3
commit 1ab1500dfd
11 changed files with 73 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/sparc/decoder.hh
View File

@@ -46,7 +46,7 @@ class Decoder
// The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
MiscReg asi;
RegVal asi;
public:
Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
@@ -93,7 +93,7 @@ class Decoder
}
void
setContext(MiscReg _asi)
setContext(RegVal _asi)
{
asi = _asi;
}

40
src/arch/sparc/faults.cc
View File

@@ -302,15 +302,15 @@ enterREDState(ThreadContext *tc)
void
doREDFault(ThreadContext *tc, TrapType tt)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
TL++;
@@ -381,15 +381,15 @@ doREDFault(ThreadContext *tc, TrapType tt)
void
doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{
MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
RegVal CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
// Increment the trap level
@@ -470,7 +470,7 @@ doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
}
void
getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
getREDVector(RegVal TT, Addr &PC, Addr &NPC)
{
//XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFF0000000ULL;
@@ -479,7 +479,7 @@ getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
}
void
getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT)
{
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
@@ -487,7 +487,7 @@ getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
}
void
getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
{
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
PC = (TBA & ~mask(15)) |
@@ -507,8 +507,8 @@ SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
// We can refer to this to see what the trap level -was-, but something
// in the middle could change it in the regfile out from under us.
MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
RegVal tl = tc->readMiscRegNoEffect(MISCREG_TL);
RegVal tt = tc->readMiscRegNoEffect(MISCREG_TT);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
@@ -731,7 +731,7 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// but does not directly affect the ASI register value in the
// architectural state. The ASI values and the context field in the
// request packet seem to have completely different uses.
MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
ASI asi = static_cast<ASI>(reg_asi);
// The SPARC DTLB code assumes that traps are executed in context

8
src/arch/sparc/faults.hh
View File

@@ -354,12 +354,12 @@ void doREDFault(ThreadContext *tc, TrapType tt);
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
MiscReg TL);
void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT,
RegVal TL);
} // namespace SparcISA

14
src/arch/sparc/isa.cc
View File

@@ -173,7 +173,7 @@ ISA::clear()
panic("Tick comparison event active when clearing the ISA object.\n");
}
MiscReg
RegVal
ISA::readMiscRegNoEffect(int miscReg) const
{
@@ -248,7 +248,7 @@ ISA::readMiscRegNoEffect(int miscReg) const
case MISCREG_TBA:
return tba;
case MISCREG_PSTATE:
return (MiscReg)pstate;
return (RegVal)pstate;
case MISCREG_TL:
return tl;
case MISCREG_PIL:
@@ -271,7 +271,7 @@ ISA::readMiscRegNoEffect(int miscReg) const
/** Hyper privileged registers */
case MISCREG_HPSTATE:
return (MiscReg)hpstate;
return (RegVal)hpstate;
case MISCREG_HTSTATE:
return htstate[tl-1];
case MISCREG_HINTP:
@@ -334,7 +334,7 @@ ISA::readMiscRegNoEffect(int miscReg) const
}
}
MiscReg
RegVal
ISA::readMiscReg(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
@@ -383,7 +383,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
}
void
ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
ISA::setMiscRegNoEffect(int miscReg, RegVal val)
{
switch (miscReg) {
// case MISCREG_Y:
@@ -564,9 +564,9 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
}
void
ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
{
MiscReg new_val = val;
RegVal new_val = val;
switch (miscReg) {
case MISCREG_ASI:

12
src/arch/sparc/isa.hh
View File

@@ -116,8 +116,8 @@ class ISA : public SimObject
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
void setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
RegVal readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
@@ -183,11 +183,11 @@ class ISA : public SimObject
public:
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
RegVal readMiscRegNoEffect(int miscReg) const;
RegVal readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, MiscReg val);
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, RegVal val);
void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const

2
src/arch/sparc/isa/decoder.isa
View File

@@ -138,7 +138,7 @@ decode OP default Unknown::unknown()
}
}
0x1: BranchN::call(30, {{
IntReg midVal;
RegVal midVal;
R15 = midVal = (Pstate.am ? (PC)<31:0> : PC);
NNPC = midVal + disp;
}},None, None, IsIndirectControl, IsCall);

14
src/arch/sparc/linux/syscalls.cc
View File

@@ -60,7 +60,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
SyscallReturn
getresuidFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
const IntReg id = htog(100);
const uint64_t id = htog(100);
int index = 0;
Addr ruid = p->getSyscallArg(tc, index);
Addr euid = p->getSyscallArg(tc, index);
@@ -68,20 +68,20 @@ getresuidFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
// Handle the EFAULT case
// Set the ruid
if (ruid) {
BufferArg ruidBuff(ruid, sizeof(IntReg));
memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
BufferArg ruidBuff(ruid, sizeof(uint64_t));
memcpy(ruidBuff.bufferPtr(), &id, sizeof(uint64_t));
ruidBuff.copyOut(tc->getMemProxy());
}
// Set the euid
if (euid) {
BufferArg euidBuff(euid, sizeof(IntReg));
memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
BufferArg euidBuff(euid, sizeof(uint64_t));
memcpy(euidBuff.bufferPtr(), &id, sizeof(uint64_t));
euidBuff.copyOut(tc->getMemProxy());
}
// Set the suid
if (suid) {
BufferArg suidBuff(suid, sizeof(IntReg));
memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
BufferArg suidBuff(suid, sizeof(uint64_t));
memcpy(suidBuff.bufferPtr(), &id, sizeof(uint64_t));
suidBuff.copyOut(tc->getMemProxy());
}
return 0;

40
src/arch/sparc/process.cc
View File

@@ -183,7 +183,7 @@ Sparc64Process::initState()
pstate.ie = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
argsInit(sizeof(IntReg), PageBytes);
argsInit(sizeof(RegVal), PageBytes);
}
template<class IntType>
@@ -441,11 +441,11 @@ Sparc32Process::argsInit(int intSize, int pageSize)
void Sparc32Process::flushWindows(ThreadContext *tc)
{
IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
MiscReg origCWP = CWP;
RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
RegVal CWP = tc->readMiscReg(MISCREG_CWP);
RegVal origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows;
while (NWindows - 2 - Cansave != 0) {
if (Otherwin) {
@@ -453,7 +453,7 @@ void Sparc32Process::flushWindows(ThreadContext *tc)
} else {
tc->setMiscReg(MISCREG_CWP, CWP);
// Do the stores
IntReg sp = tc->readIntReg(StackPointerReg);
RegVal sp = tc->readIntReg(StackPointerReg);
for (int index = 16; index < 32; index++) {
uint32_t regVal = tc->readIntReg(index);
regVal = htog(regVal);
@@ -476,11 +476,11 @@ void Sparc32Process::flushWindows(ThreadContext *tc)
void
Sparc64Process::flushWindows(ThreadContext *tc)
{
IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
MiscReg origCWP = CWP;
RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
RegVal CWP = tc->readMiscReg(MISCREG_CWP);
RegVal origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows;
while (NWindows - 2 - Cansave != 0) {
if (Otherwin) {
@@ -488,9 +488,9 @@ Sparc64Process::flushWindows(ThreadContext *tc)
} else {
tc->setMiscReg(MISCREG_CWP, CWP);
// Do the stores
IntReg sp = tc->readIntReg(StackPointerReg);
RegVal sp = tc->readIntReg(StackPointerReg);
for (int index = 16; index < 32; index++) {
IntReg regVal = tc->readIntReg(index);
RegVal regVal = tc->readIntReg(index);
regVal = htog(regVal);
if (!tc->getMemProxy().tryWriteBlob(
sp + 2047 + (index - 16) * 8, (uint8_t *)&regVal, 8)) {
@@ -508,7 +508,7 @@ Sparc64Process::flushWindows(ThreadContext *tc)
tc->setMiscReg(MISCREG_CWP, origCWP);
}
IntReg
RegVal
Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -516,13 +516,13 @@ Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
}
void
Sparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
Sparc32Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
}
IntReg
RegVal
Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -530,7 +530,7 @@ Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
}
void
Sparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
Sparc64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, val);
@@ -547,7 +547,7 @@ SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
// no error, clear XCC.C
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
IntReg val = sysret.returnValue();
RegVal val = sysret.returnValue();
if (pstate.am)
val = bits(val, 31, 0);
tc->setIntReg(ReturnValueReg, val);
@@ -555,7 +555,7 @@ SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
// got an error, set XCC.C
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) | 0x11);
IntReg val = sysret.errnoValue();
RegVal val = sysret.errnoValue();
if (pstate.am)
val = bits(val, 31, 0);
tc->setIntReg(ReturnValueReg, val);

8
src/arch/sparc/process.hh
View File

@@ -109,11 +109,11 @@ class Sparc32Process : public SparcProcess
void flushWindows(ThreadContext *tc);
SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
RegVal getSyscallArg(ThreadContext *tc, int &i);
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
void setSyscallArg(ThreadContext *tc, int i, RegVal val);
};
class Sparc64Process : public SparcProcess
@@ -153,11 +153,11 @@ class Sparc64Process : public SparcProcess
void flushWindows(ThreadContext *tc);
SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
RegVal getSyscallArg(ThreadContext *tc, int &i);
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
void setSyscallArg(ThreadContext *tc, int i, RegVal val);
};
#endif // __SPARC_PROCESS_HH__

5
src/arch/sparc/registers.hh
View File

@@ -45,11 +45,6 @@ using SparcISAInst::MaxInstSrcRegs;
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
typedef RegVal IntReg;
typedef RegVal MiscReg;
typedef FloatRegVal FloatReg;
typedef RegVal FloatRegBits;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

4
src/arch/sparc/ua2005.cc
View File

@@ -88,7 +88,7 @@ getMiscRegName(RegIndex index)
}
void
ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
@@ -242,7 +242,7 @@ ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
}
}
MiscReg
RegVal
ISA::readFSReg(int miscReg, ThreadContext * tc)
{
uint64_t temp;