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gem5/src/arch/riscv
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Gabe Black a78abf07b7 riscv: Implement an SE workload for Linux. 
Change-Id: Ieb7058007e56ce0c8d153c1853e4b92237e98ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34156
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-29 01:34:41 +00:00
..
bare_metal
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
insts
arch-riscv: Fix disassembling of CSR instructions
2020-08-19 05:03:46 +00:00
isa
arch-riscv: Replace any getDTBPtr/getITBPtr usage
2020-10-27 09:46:08 +00:00
linux
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
decoder.cc
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
decoder.hh
arch: Create a base class for decoders.
2020-08-20 01:07:13 +00:00
faults.cc
arch,cpu,sim: Route system calls through the workload.
2020-09-20 07:26:42 +00:00
faults.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
fs_workload.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
idle_event.cc
arch,cpu,sim: Eliminate the now empty kernel statistics classes.
2020-06-17 19:54:41 +00:00
idle_event.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
interrupts.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
interrupts.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
isa_traits.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
isa.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
isa.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
locked_mem.cc
riscv: fix AMO, LR and SC instructions
2019-02-08 15:27:04 +00:00
locked_mem.hh
base, sim, mem, arch: Remove the dummy CPU in NULL
2020-09-14 08:52:40 +00:00
mmu.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mmu.hh
arch-riscv: Replace any getDTBPtr/getITBPtr usage
2020-10-27 09:46:08 +00:00
pagetable_walker.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
pagetable_walker.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
pagetable.cc
arch-riscv: added TLB and page table walker.
2020-04-29 11:41:55 +00:00
pagetable.hh
misc: Fix a few accidental transitive includes.
2020-10-21 22:56:14 +00:00
pra_constants.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
process.cc
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
process.hh
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
pseudo_inst.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
registers.hh
misc: Fix a few accidental transitive includes.
2020-10-21 22:56:14 +00:00
remote_gdb.cc
arch-riscv: Replace any getDTBPtr/getITBPtr usage
2020-10-27 09:46:08 +00:00
remote_gdb.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvFsWorkload.py
arch,sim,kern,dev,cpu: Create a Workload SimObject.
2020-04-22 00:22:28 +00:00
RiscvInterrupts.py
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvISA.py
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
RiscvMMU.py
misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
2020-10-21 09:33:39 +00:00
RiscvSeWorkload.py
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
RiscvTLB.py
arch: update port terminology
2020-08-26 16:48:13 +00:00
SConscript
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
SConsopts
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
se_workload.cc
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
se_workload.hh
riscv: Implement an SE workload for Linux.
2020-10-29 01:34:41 +00:00
stacktrace.hh
arch,cpu: Consolidate most of the StackTrace classes into a base class.
2020-07-11 00:24:38 +00:00
tlb.cc
arch-riscv: Replace any getDTBPtr/getITBPtr usage
2020-10-27 09:46:08 +00:00
tlb.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
types.hh
riscv: Delete authors lists from riscv files.
2020-02-18 03:36:09 +00:00
utility.hh
arch-riscv: Add float registers in copyRegs
2020-08-21 00:51:26 +00:00