5d5f53378b
Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25451 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
110 lines
3.4 KiB
C++
110 lines
3.4 KiB
C++
/*
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* Copyright (c) 2012 Google
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* Copyright (c) The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/riscv/decoder.hh"
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#include "arch/riscv/types.hh"
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#include "debug/Decode.hh"
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namespace RiscvISA
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{
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static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1;
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static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4;
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void Decoder::reset()
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{
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aligned = true;
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mid = false;
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more = true;
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emi = 0;
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instDone = false;
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}
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void
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Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
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{
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inst = letoh(inst);
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DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
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fetchPC);
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bool aligned = pc.pc() % sizeof(MachInst) == 0;
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if (aligned) {
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emi = inst;
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if (compressed(emi))
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emi &= LowerBitMask;
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more = !compressed(emi);
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instDone = true;
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} else {
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if (mid) {
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assert((emi & UpperBitMask) == 0);
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emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
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mid = false;
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more = false;
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instDone = true;
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} else {
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emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
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mid = !compressed(emi);
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more = true;
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instDone = compressed(emi);
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}
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}
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}
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StaticInstPtr
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Decoder::decode(ExtMachInst mach_inst, Addr addr)
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{
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DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
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mach_inst, addr);
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if (instMap.find(mach_inst) != instMap.end())
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return instMap[mach_inst];
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else {
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StaticInstPtr si = decodeInst(mach_inst);
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instMap[mach_inst] = si;
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return si;
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}
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}
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StaticInstPtr
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Decoder::decode(RiscvISA::PCState &nextPC)
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{
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if (!instDone)
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return nullptr;
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instDone = false;
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if (compressed(emi)) {
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nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2);
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} else {
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nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
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}
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return decode(emi, nextPC.instAddr());
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}
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}
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