Giacomo Travaglini 8e5e603041 misc: Fix VecPredReg coding style ...

* get_bits -> getBits
* set_bits -> setBits
* set_raw -> setRaw
* get_raw -> getRaw

Change-Id: I57c0217dc399b7e1c5b007ed862d7ed221d5ac0b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44505
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-04-15 08:15:45 +00:00

..

amdgpu

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

arm

misc: Fix VecPredReg coding style

2021-04-15 08:15:45 +00:00

gcn3

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

generic

misc: Fix VecPredReg coding style

2021-04-15 08:15:45 +00:00

isa_parser

base,misc: Collapse and eliminate the ULL and LL macros.

2021-03-11 04:14:17 +00:00

mips

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

null

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

power

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

riscv

arch-riscv: Fix braces around scalar initializer

2021-04-10 23:28:16 +00:00

sparc

arch,cpu,gpu-compute: Further simplify VecRegContainer.

2021-04-10 07:31:23 +00:00

x86

arch-x86: Fixed locked cmpxchg8b allows reordering

2021-04-12 08:01:50 +00:00

micro_asm_test.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

micro_asm.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

SConscript

scons: More narrowly target -Wno-self-assign.

2021-04-03 05:52:24 +00:00

SConsopts

scons: Pull domain specific build setup out of SConstruct.

2021-04-03 01:18:17 +00:00