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8c98dcb7cf50c0602e3f4091469848c77601e740
gem5/src/arch
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Yu-Cheng Chang 5d3f1c3316 arch-riscv: Add rvZext to BranchTarget (#1173)
Ensure the upper xlen bits are all zeros

Change-Id: Id81330eced907d21320bc1af85ad38fb6e95f6b1
2024-06-03 10:03:51 -07:00
..
amdgpu
arch-vega: Implement literals for 64b dest operands
2024-05-31 13:41:46 -07:00
arm
arch-arm: Fix memory attributes of table walks (#1180)
2024-05-29 08:07:44 -07:00
generic
arch-generic: Avoid out-of-memory errors for bad semihosting calls (#1143)
2024-05-16 10:28:10 -07:00
isa_parser
arch: Fix inst flag of RISC-V vector store macro instructions
2023-12-12 17:04:31 +08:00
mips
misc: Serialize the ISA as a string in the checkpoint
2024-03-04 17:51:40 +00:00
null
scons: Update the Kconfig build options
2023-11-23 08:26:11 +08:00
power
misc: Serialize the ISA as a string in the checkpoint
2024-03-04 17:51:40 +00:00
riscv
arch-riscv: Add rvZext to BranchTarget (#1173)
2024-06-03 10:03:51 -07:00
sparc
arch-riscv,sim: m5ops argument / return fix for 32 bit RISC-V (#900)
2024-04-08 10:09:17 -07:00
x86
arch-x86: set AF=0 when logical instructions execute (#1171)
2024-05-29 08:04:44 -07:00
Kconfig
scons: Update the Kconfig build options
2023-11-23 08:26:11 +08:00
micro_asm_test.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
micro_asm.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
SConscript
arch-gcn3: Remove all GCN3 files
2024-01-17 10:44:44 -06:00
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