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arch-riscv: Add rvZext to BranchTarget (#1173)

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Ensure the upper xlen bits are all zeros

Change-Id: Id81330eced907d21320bc1af85ad38fb6e95f6b1
This commit is contained in:
Yu-Cheng Chang
2024-06-04 01:03:51 +08:00
committed by GitHub
parent fe8daa85d6
commit 5d3f1c3316
2 changed files with 4 additions and 3 deletions
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2
src/arch/riscv/isa/formats/compressed.isa
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@@ -173,7 +173,7 @@ def template CJumpExecute {{
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCStateBase *pc_ptr = tc->pcState().clone();
pc_ptr->as<PCState>().set(tc->getReg(srcRegIdx(0)) & ~0x1);
pc_ptr->as<PCState>().set(rvZext(tc->getReg(srcRegIdx(0)) & ~0x1));
return std::unique_ptr<PCStateBase>{pc_ptr};
}

5
src/arch/riscv/isa/formats/standard.isa
View File

@@ -199,7 +199,7 @@ def template BranchExecute {{
{
auto &rpc = branch_pc.as<RiscvISA::PCState>();
std::unique_ptr<PCState> npc(dynamic_cast<PCState*>(rpc.clone()));
npc->set(rpc.pc() + imm);
npc->set(rvZext(rpc.pc() + imm));
return npc;
}
@@ -306,7 +306,8 @@ def template JumpExecute {{
%(class_name)s::branchTarget(ThreadContext *tc) const
{
PCStateBase *pc_ptr = tc->pcState().clone();
pc_ptr->as<PCState>().set((tc->getReg(srcRegIdx(0)) + imm) & ~0x1);
pc_ptr->as<PCState>().set(
rvZext((tc->getReg(srcRegIdx(0)) + imm) & ~0x1));
return std::unique_ptr<PCStateBase>{pc_ptr};
}