From 5d3f1c3316f8588fd332a1a936ba184499117918 Mon Sep 17 00:00:00 2001
From: Yu-Cheng Chang <rogerycchang@google.com>
Date: Tue, 4 Jun 2024 01:03:51 +0800
Subject: [PATCH] arch-riscv: Add rvZext to BranchTarget (#1173)

Ensure the upper xlen bits are all zeros

Change-Id: Id81330eced907d21320bc1af85ad38fb6e95f6b1
---
 src/arch/riscv/isa/formats/compressed.isa | 2 +-
 src/arch/riscv/isa/formats/standard.isa   | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index 607415b424..8d6a125ef1 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -173,7 +173,7 @@ def template CJumpExecute {{
     %(class_name)s::branchTarget(ThreadContext *tc) const
     {
         PCStateBase *pc_ptr = tc->pcState().clone();
-        pc_ptr->as<PCState>().set(tc->getReg(srcRegIdx(0)) & ~0x1);
+        pc_ptr->as<PCState>().set(rvZext(tc->getReg(srcRegIdx(0)) & ~0x1));
         return std::unique_ptr<PCStateBase>{pc_ptr};
     }
 
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index b201a90fef..83b135daf2 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -199,7 +199,7 @@ def template BranchExecute {{
     {
         auto &rpc = branch_pc.as<RiscvISA::PCState>();
         std::unique_ptr<PCState> npc(dynamic_cast<PCState*>(rpc.clone()));
-        npc->set(rpc.pc() + imm);
+        npc->set(rvZext(rpc.pc() + imm));
         return npc;
     }
 
@@ -306,7 +306,8 @@ def template JumpExecute {{
     %(class_name)s::branchTarget(ThreadContext *tc) const
     {
         PCStateBase *pc_ptr = tc->pcState().clone();
-        pc_ptr->as<PCState>().set((tc->getReg(srcRegIdx(0)) + imm) & ~0x1);
+        pc_ptr->as<PCState>().set(
+            rvZext((tc->getReg(srcRegIdx(0)) + imm) & ~0x1));
         return std::unique_ptr<PCStateBase>{pc_ptr};
     }