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arch-vega: Implement literals for 64b dest operands

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This feature has been available since Vega10 but was never implemented.
MI300 adds a few new instructions that make use of this more often
(e.g., v_mov_b64).

Change-Id: Ieeb7834462b76d77c0030f49622d0de09f90c9e4
This commit is contained in:
Matthew Poremba
2024-05-31 13:40:20 -07:00
parent 6c8caf83c6
commit 00dcd5b0bc
1 changed files with 23 additions and 1 deletions
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24
src/arch/amdgpu/vega/operand.hh
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@@ -579,8 +579,30 @@ namespace VegaISA
case REG_SRC_SWDA:
case REG_SRC_DPP:
case REG_SRC_LITERAL:
assert(NumDwords == 1);
/**
* From the Vega specification:
* When a literal constant is used with a 64 bit instruction,
* the literal is expanded to 64 bits by: padding the LSBs
* with zeros for floats, padding the MSBs with zeros for
* unsigned ints, and by sign-extending signed ints.
*/
srfData[0] = _gpuDynInst->srcLiteral();
if constexpr (NumDwords == 2) {
if constexpr (std::is_integral_v<DataType>) {
if constexpr (std::is_signed_v<DataType>) {
if (bits(srfData[0], 31, 31) == 1) {
srfData[1] = 0xffffffff;
} else {
srfData[1] = 0;
}
} else {
srfData[1] = 0;
}
} else {
srfData[1] = _gpuDynInst->srcLiteral();
srfData[0] = 0;
}
}
break;
case REG_SHARED_BASE:
{