From 00dcd5b0bc9a817f7bf64bbac48f97c3a7a19c00 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Fri, 31 May 2024 13:40:20 -0700 Subject: [PATCH] arch-vega: Implement literals for 64b dest operands This feature has been available since Vega10 but was never implemented. MI300 adds a few new instructions that make use of this more often (e.g., v_mov_b64). Change-Id: Ieeb7834462b76d77c0030f49622d0de09f90c9e4 --- src/arch/amdgpu/vega/operand.hh | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/arch/amdgpu/vega/operand.hh b/src/arch/amdgpu/vega/operand.hh index 593f0e34fd..1bb9b43d1f 100644 --- a/src/arch/amdgpu/vega/operand.hh +++ b/src/arch/amdgpu/vega/operand.hh @@ -579,8 +579,30 @@ namespace VegaISA case REG_SRC_SWDA: case REG_SRC_DPP: case REG_SRC_LITERAL: - assert(NumDwords == 1); + /** + * From the Vega specification: + * When a literal constant is used with a 64 bit instruction, + * the literal is expanded to 64 bits by: padding the LSBs + * with zeros for floats, padding the MSBs with zeros for + * unsigned ints, and by sign-extending signed ints. + */ srfData[0] = _gpuDynInst->srcLiteral(); + if constexpr (NumDwords == 2) { + if constexpr (std::is_integral_v) { + if constexpr (std::is_signed_v) { + if (bits(srfData[0], 31, 31) == 1) { + srfData[1] = 0xffffffff; + } else { + srfData[1] = 0; + } + } else { + srfData[1] = 0; + } + } else { + srfData[1] = _gpuDynInst->srcLiteral(); + srfData[0] = 0; + } + } break; case REG_SHARED_BASE: {