Cui Jin 8c3658939d arch-riscv: fix the wrong cause register setting ...

The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.

Minor bug is for the mpie is suppossed to be set to the value of
old mie.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-858

Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-01-06 01:18:15 +00:00

..

arm

scons,fastmodel: Change how ARM license slots are throttled.

2020-12-21 21:53:40 +00:00

gcn3

arch-gcn3: Explicitly sign-extend simm16

2020-11-17 17:08:24 +00:00

generic

arch: Move many of the generic files outside an NULL guard.

2020-10-29 20:23:35 +00:00

isa_parser

arch: Add a mechanism to pad the src or dest reg index arrays.

2021-01-05 07:33:01 +00:00

mips

mips: Convert MIPS to use local register index storage.

2020-11-24 06:25:23 +00:00

null

base, sim, mem, arch: Remove the dummy CPU in NULL

2020-09-14 08:52:40 +00:00

power

power: Convert POWER to use local reg index storage.

2020-11-28 02:05:38 +00:00

riscv

arch-riscv: fix the wrong cause register setting

2021-01-06 01:18:15 +00:00

sparc

sparc: Convert SPARC to use local register index storage.

2020-11-24 06:25:14 +00:00

x86

x86: Fix some comments in x86 KVM process initialization.

2020-12-17 03:30:20 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch,sim: Handle KVM SE page faults with workload events.

2020-10-29 20:23:26 +00:00