derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sparc: Convert SPARC to use local register index storage.

Browse Source 
Once all ISAs are converted, the base StaticInst class will be able to
drop its local arrays, and will no longer need to know what the global
maximum number of source or destination registers is for a given
instruction.

Most of the convertion was very simple and just involved adding tags to
declare and install the register arrays in all the class definitions.
Since SPARC has a relatively simple ISA definition, there weren't many
places that needed to be updated.

The exception was the BlockMem template, which was declaring the microop
classes within the body of the macroop. That was ok when those
declarations didn't need anything other than the name of their parent,
but now they also need to know how big to declare their arrays based on
their actual implementation.

To facilitate that, and to significantly streamline the definition of
the macroop class, the microop class definitions were moved to their own
template, and only the declaration was left in the parent class.

Change-Id: I09e6b1d1041c6a0aeaee63ce5f9a18cf482b6203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36879
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-11-01 03:52:41 -08:00
parent 2b5b472667
commit 05f4da7600
5 changed files with 62 additions and 114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/arch/sparc/isa/formats/basic.isa
View File

@@ -31,6 +31,9 @@ def template BasicDeclare {{
*/
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -45,6 +48,9 @@ def template FpBasicDeclare {{
*/
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -60,6 +66,9 @@ def template BasicDeclareWithMnemonic {{
*/
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
// Constructor.
%(class_name)s(const char *mnemonic, ExtMachInst machInst);
@@ -72,6 +81,7 @@ def template BasicConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -81,6 +91,7 @@ def template BasicConstructorWithMnemonic {{
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst) :
%(base_class)s(mnemonic, machInst, %(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};

3
src/arch/sparc/isa/formats/mem/basicmem.isa
View File

@@ -37,6 +37,9 @@ def template MemDeclare {{
*/
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
/// Constructor.

158
src/arch/sparc/isa/formats/mem/blockmem.isa
View File

@@ -30,120 +30,43 @@
//
def template BlockMemDeclare {{
/**
* Static instruction class for a block memory operation
*/
class %(class_name)s : public %(base_class)s
{
public:
// Constructor
%(class_name)s(ExtMachInst machInst);
/**
* Static instruction class for a block memory operation
*/
class %(class_name)s : public %(base_class)s
{
public:
// Constructor
%(class_name)s(ExtMachInst machInst);
protected:
class %(class_name)s_0 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_0(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
protected:
class %(class_name)s_0;
class %(class_name)s_1;
class %(class_name)s_2;
class %(class_name)s_3;
class %(class_name)s_4;
class %(class_name)s_5;
class %(class_name)s_6;
class %(class_name)s_7;
};
}};
class %(class_name)s_1 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_1(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
def template BlockMemMicroDeclare {{
class %(class_name)s::%(class_name)s_%(micro_pc)s :
public %(base_class)sMicro
{
private:
%(reg_idx_arr_decl)s;
class %(class_name)s_2 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_2(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
public:
// Constructor
%(class_name)s_%(micro_pc)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
class %(class_name)s_3 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_3(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
class %(class_name)s_4 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_4(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
class %(class_name)s_5 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_5(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
class %(class_name)s_6 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_6(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
class %(class_name)s_7 : public %(base_class)sMicro
{
public:
// Constructor
%(class_name)s_7(ExtMachInst machInst);
Fault execute(ExecContext *,
Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
Trace::InstRecord *) const override;
};
};
}};
// Basic instruction class constructor template.
@@ -170,6 +93,7 @@ def template BlockMemMicroConstructor {{
%(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
machInst, %(op_class)s, %(micro_pc)s * 8)
{
%(set_reg_idx_arr)s;
%(constructor)s;
%(set_flags)s;
}
@@ -184,9 +108,12 @@ let {{
addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
addrCalcImm = 'EA = Rs1 + imm + offset;'
iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm',
code, opt_flags)
header_output = BlockMemDeclare.subst(iop) + \
BlockMemDeclare.subst(iop_imm)
decoder_output = BlockMemConstructor.subst(iop) + \
BlockMemConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)
matcher = re.compile(r'Frd_N')
exec_output = ''
@@ -195,7 +122,8 @@ let {{
if (microPc == 7):
flag_code = "flags[IsLastMicroop] = true;"
elif (microPc == 0):
flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;"
flag_code = "flags[IsDelayedCommit] = true; " \
"flags[IsFirstMicroop] = true;"
else:
flag_code = "flags[IsDelayedCommit] = true;"
pcedCode = matcher.sub("Frd_%d" % microPc, code)
@@ -209,6 +137,8 @@ let {{
"fault_check": faultCode, "micro_pc": microPc,
"set_flags": flag_code, "EA_trunc" : TruncateEA},
opt_flags)
header_output += BlockMemMicroDeclare.subst(iop)
header_output += BlockMemMicroDeclare.subst(iop_imm)
decoder_output += BlockMemMicroConstructor.subst(iop)
decoder_output += BlockMemMicroConstructor.subst(iop_imm)
exec_output += doDualSplitExecute(

3
src/arch/sparc/isa/formats/nop.isa
View File

@@ -34,6 +34,9 @@ def template NopDeclare {{
*/
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
%(class_name)s(ExtMachInst machInst);
};

1
src/arch/sparc/isa/formats/priv.isa
View File

@@ -33,6 +33,7 @@ def template ControlRegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, "%(reg_name)s")
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};