Giacomo Travaglini 89323c5112 arch-arm: Group testTranslation and finalizeTranslation together ...

They both make final checks to the VA->PA translation before
relinquishing control back to the translate client (usually
CPU code)

Change-Id: Ib0a9da25404248c22c6a240817d2f50f0913fdf7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

2024-04-24 18:12:36 +01:00

..

amdgpu

arch-vega: Fix string check warnings on fast build

2024-04-14 12:22:57 -07:00

arm

arch-arm: Group testTranslation and finalizeTranslation together

2024-04-24 18:12:36 +01:00

generic

arch: Add getIsaName in BaseISA (#975)

2024-03-28 13:27:32 +00:00

isa_parser

arch: Fix inst flag of RISC-V vector store macro instructions

2023-12-12 17:04:31 +08:00

mips

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

null

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

power

misc: Serialize the ISA as a string in the checkpoint

2024-03-04 17:51:40 +00:00

riscv

cpu,arch-arm,arch-riscv: adding new instruction types to RISC-V (#589)

2024-04-11 10:15:56 -07:00

sparc

arch-riscv,sim: m5ops argument / return fix for 32 bit RISC-V (#900)

2024-04-08 10:09:17 -07:00

x86

arch-x86: Use mbits function for clarity

2024-04-15 22:49:41 -05:00

Kconfig

scons: Update the Kconfig build options

2023-11-23 08:26:11 +08:00

micro_asm_test.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

micro_asm.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

SConscript

arch-gcn3: Remove all GCN3 files

2024-01-17 10:44:44 -06:00