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cpu,arch-arm,arch-riscv: adding new instruction types to RISC-V (#589)

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This commit adds more detailed instruction types for RISC-V Vector.
Concretely, it substitutes VectorIntegerArith, VectorFloatArith,
VectorIntegerReduce and VectorFloatReduce with more specific types
related to the operation that each instruction (e.g., VectorIntegerAdd
or VectorIntegerMult).

Additionaly, fixes two RISC-V instruction types (VectorXXX) that were
used in ARM SVE, placing the proper SimdXXX ones.

Change-Id: I31774fa6a7cd249abfffec68d11d3d77f08ad70b

CC @adriaarmejach
This commit is contained in:
Ivana Mitrovic
2024-04-11 10:15:56 -07:00
committed by GitHub
parent 3b5ae7b4d1 c91d1253de
commit db1c336237
10 changed files with 532 additions and 525 deletions
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8
src/arch/arm/isa/insts/sve.isa
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@@ -4426,19 +4426,19 @@ let {{
# ADCLT
adcltCode = 'res = srcElem1 + srcElem2 + carryIn;'
sveTerInstUnpred('adclt', 'Adclt', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('adclt', 'Adclt', 'SimdAddOp', unsignedTypes,
adcltCode, isTop=True, isAdd=True)
# ADCLB
adclbCode = 'res = srcElem1 + srcElem2 + carryIn;'
sveTerInstUnpred('adclb', 'Adclb', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('adclb', 'Adclb', 'SimdAddOp', unsignedTypes,
adclbCode, isTop=False, isAdd=True)
# SBCLT
sbcltCode = 'res = srcElem1 + ~(srcElem2) + carryIn;'
sveTerInstUnpred('sbclt', 'Sbclt', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('sbclt', 'Sbclt', 'SimdAddOp', unsignedTypes,
sbcltCode, isTop=True, isAdd=False)
# SBCLB
sbclbCode = 'res = srcElem1 + ~(srcElem2) + carryIn;'
sveTerInstUnpred('sbclb', 'Sbclb', 'VectorIntegerArithOp', unsignedTypes,
sveTerInstUnpred('sbclb', 'Sbclb', 'SimdAddOp', unsignedTypes,
sbclbCode, isTop=False, isAdd=False)
mmlaCode = ('destElem += srcElemA * srcElemB')
# SMMLA (vectors)

8
src/arch/riscv/insts/vector.cc
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@@ -414,7 +414,7 @@ VMvWholeMicroInst::generateDisassembly(Addr pc,
VMaskMergeMicroInst::VMaskMergeMicroInst(ExtMachInst extMachInst,
uint8_t _dstReg, uint8_t _numSrcs, uint32_t _vlen, size_t _elemSize)
: VectorArithMicroInst("vmask_mv_micro", extMachInst,
VectorIntegerArithOp, 0, 0),
SimdAddOp, 0, 0),
vlen(_vlen),
elemSize(_elemSize)
{
@@ -503,7 +503,7 @@ VxsatMicroInst::generateDisassembly(Addr pc,
VlFFTrimVlMicroOp::VlFFTrimVlMicroOp(ExtMachInst _machInst, uint32_t _microVl,
uint32_t _microIdx, uint32_t _vlen, std::vector<StaticInstPtr>& _microops)
: VectorMicroInst("vlff_trimvl_v_micro", _machInst, VectorConfigOp,
: VectorMicroInst("vlff_trimvl_v_micro", _machInst, SimdConfigOp,
_microVl, _microIdx, _vlen),
microops(_microops)
{
@@ -618,7 +618,7 @@ VlSegDeIntrlvMicroInst::VlSegDeIntrlvMicroInst(ExtMachInst extMachInst, uint32_t
uint32_t _microIdx, uint32_t _numMicroops,
uint32_t _field, uint32_t _vlen, uint32_t _sizeOfElement)
: VectorArithMicroInst("vlseg_deintrlv_micro", extMachInst,
VectorIntegerArithOp, 0, 0),
SimdAddOp, 0, 0),
vlen(_vlen)
{
setRegIdxArrays(
@@ -715,7 +715,7 @@ VsSegIntrlvMicroInst::VsSegIntrlvMicroInst(ExtMachInst extMachInst, uint32_t _mi
uint32_t _microIdx, uint32_t _numMicroops,
uint32_t _field, uint32_t _vlen, uint32_t _sizeOfElement)
: VectorArithMicroInst("vsseg_reintrlv_micro", extMachInst,
VectorIntegerArithOp, 0, 0),
SimdAddOp, 0, 0),
vlen(_vlen)
{
setRegIdxArrays(

2
src/arch/riscv/insts/vector.hh
View File

@@ -569,7 +569,7 @@ class VxsatMicroInst : public VectorArithMicroInst
public:
VxsatMicroInst(bool* Vxsat, ExtMachInst extMachInst)
: VectorArithMicroInst("vxsat_micro", extMachInst,
VectorIntegerArithOp, 0, 0)
SimdMiscOp, 0, 0)
{
vxsat = Vxsat;
}

860
src/arch/riscv/isa/decoder.isa
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File diff suppressed because it is too large Load Diff

2
src/arch/riscv/isa/templates/vector_mem.isa
View File

@@ -82,7 +82,7 @@ def template VleConstructor {{
micro_vl = std::min(remaining_vl -= micro_vlmax, micro_vlmax);
}
if (_opClass == VectorUnitStrideFaultOnlyFirstLoadOp) {
if (_opClass == SimdUnitStrideFaultOnlyFirstLoadOp) {
microop = new VlFFTrimVlMicroOp(_machInst, this->vl, num_microops,
vlen, microops);
this->microops.push_back(microop);

37
src/cpu/FuncUnit.py
View File

@@ -100,27 +100,22 @@ class OpClass(Enum):
"FloatMemWrite",
"IprAccess",
"InstPrefetch",
"VectorUnitStrideLoad",
"VectorUnitStrideStore",
"VectorUnitStrideSegmentedStore",
"VectorUnitStrideMaskLoad",
"VectorUnitStrideMaskStore",
"VectorStridedLoad",
"VectorStridedStore",
"VectorIndexedLoad",
"VectorIndexedStore",
"VectorUnitStrideFaultOnlyFirstLoad",
"VectorWholeRegisterLoad",
"VectorWholeRegisterStore",
"VectorIntegerArith",
"VectorUnitStrideSegmentedLoad",
"VectorFloatArith",
"VectorFloatConvert",
"VectorIntegerReduce",
"VectorFloatReduce",
"VectorMisc",
"VectorIntegerExtension",
"VectorConfig",
"SimdUnitStrideLoad",
"SimdUnitStrideStore",
"SimdUnitStrideMaskLoad",
"SimdUnitStrideMaskStore",
"SimdStridedLoad",
"SimdStridedStore",
"SimdIndexedLoad",
"SimdIndexedStore",
"SimdWholeRegisterLoad",
"SimdWholeRegisterStore",
"SimdUnitStrideFaultOnlyFirstLoad",
"SimdUnitStrideSegmentedLoad",
"SimdUnitStrideSegmentedStore",
"SimdExt",
"SimdFloatExt",
"SimdConfig",
]

51
src/cpu/minor/BaseMinorCPU.py
View File

@@ -219,6 +219,10 @@ class MinorDefaultFloatSimdFU(MinorFU):
"Matrix",
"MatrixMov",
"MatrixOP",
"SimdExt",
"SimdFloatExt",
"SimdFloatCvt",
"SimdConfig",
]
)
@@ -234,7 +238,23 @@ class MinorDefaultPredFU(MinorFU):
class MinorDefaultMemFU(MinorFU):
opClasses = minorMakeOpClassSet(
["MemRead", "MemWrite", "FloatMemRead", "FloatMemWrite"]
[
"MemRead",
"MemWrite",
"FloatMemRead",
"FloatMemWrite",
"SimdUnitStrideLoad",
"SimdUnitStrideStore",
"SimdUnitStrideMaskLoad",
"SimdUnitStrideMaskStore",
"SimdStridedLoad",
"SimdStridedStore",
"SimdIndexedLoad",
"SimdIndexedStore",
"SimdUnitStrideFaultOnlyFirstLoad",
"SimdWholeRegisterLoad",
"SimdWholeRegisterStore",
]
)
timings = [
MinorFUTiming(
@@ -249,34 +269,6 @@ class MinorDefaultMiscFU(MinorFU):
opLat = 1
class MinorDefaultVecFU(MinorFU):
opClasses = minorMakeOpClassSet(
[
"VectorUnitStrideLoad",
"VectorUnitStrideStore",
"VectorUnitStrideMaskLoad",
"VectorUnitStrideMaskStore",
"VectorStridedLoad",
"VectorStridedStore",
"VectorIndexedLoad",
"VectorIndexedStore",
"VectorUnitStrideFaultOnlyFirstLoad",
"VectorUnitStrideSegmentedLoad",
"VectorWholeRegisterLoad",
"VectorWholeRegisterStore",
"VectorIntegerArith",
"VectorFloatArith",
"VectorFloatConvert",
"VectorIntegerReduce",
"VectorFloatReduce",
"VectorMisc",
"VectorIntegerExtension",
"VectorConfig",
]
)
opLat = 1
class MinorDefaultFUPool(MinorFUPool):
funcUnits = [
MinorDefaultIntFU(),
@@ -287,7 +279,6 @@ class MinorDefaultFUPool(MinorFUPool):
MinorDefaultPredFU(),
MinorDefaultMemFU(),
MinorDefaultMiscFU(),
MinorDefaultVecFU(),
]

35
src/cpu/o3/FuncUnitConfig.py
View File

@@ -106,6 +106,9 @@ class SIMD_Unit(FUDesc):
OpDesc(opClass="SimdReduceCmp"),
OpDesc(opClass="SimdFloatReduceAdd"),
OpDesc(opClass="SimdFloatReduceCmp"),
OpDesc(opClass="SimdExt"),
OpDesc(opClass="SimdFloatExt"),
OpDesc(opClass="SimdConfig"),
]
count = 4
@@ -116,12 +119,29 @@ class PredALU(FUDesc):
class ReadPort(FUDesc):
opList = [OpDesc(opClass="MemRead"), OpDesc(opClass="FloatMemRead")]
opList = [
OpDesc(opClass="MemRead"),
OpDesc(opClass="FloatMemRead"),
OpDesc(opClass="SimdUnitStrideLoad"),
OpDesc(opClass="SimdUnitStrideMaskLoad"),
OpDesc(opClass="SimdStridedLoad"),
OpDesc(opClass="SimdIndexedLoad"),
OpDesc(opClass="SimdUnitStrideFaultOnlyFirstLoad"),
OpDesc(opClass="SimdWholeRegisterLoad"),
]
count = 0
class WritePort(FUDesc):
opList = [OpDesc(opClass="MemWrite"), OpDesc(opClass="FloatMemWrite")]
opList = [
OpDesc(opClass="MemWrite"),
OpDesc(opClass="FloatMemWrite"),
OpDesc(opClass="SimdUnitStrideStore"),
OpDesc(opClass="SimdUnitStrideMaskStore"),
OpDesc(opClass="SimdStridedStore"),
OpDesc(opClass="SimdIndexedStore"),
OpDesc(opClass="SimdWholeRegisterStore"),
]
count = 0
@@ -131,6 +151,17 @@ class RdWrPort(FUDesc):
OpDesc(opClass="MemWrite"),
OpDesc(opClass="FloatMemRead"),
OpDesc(opClass="FloatMemWrite"),
OpDesc(opClass="SimdUnitStrideLoad"),
OpDesc(opClass="SimdUnitStrideStore"),
OpDesc(opClass="SimdUnitStrideMaskLoad"),
OpDesc(opClass="SimdUnitStrideMaskStore"),
OpDesc(opClass="SimdStridedLoad"),
OpDesc(opClass="SimdStridedStore"),
OpDesc(opClass="SimdIndexedLoad"),
OpDesc(opClass="SimdIndexedStore"),
OpDesc(opClass="SimdUnitStrideFaultOnlyFirstLoad"),
OpDesc(opClass="SimdWholeRegisterLoad"),
OpDesc(opClass="SimdWholeRegisterStore"),
]
count = 4

49
src/cpu/op_class.hh
View File

@@ -108,35 +108,30 @@ static const OpClass MemReadOp = enums::MemRead;
static const OpClass MemWriteOp = enums::MemWrite;
static const OpClass FloatMemReadOp = enums::FloatMemRead;
static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
static const OpClass SimdUnitStrideLoadOp = enums::SimdUnitStrideLoad;
static const OpClass SimdUnitStrideStoreOp = enums::SimdUnitStrideStore;
static const OpClass SimdUnitStrideMaskLoadOp
= enums::SimdUnitStrideMaskLoad;
static const OpClass SimdUnitStrideMaskStoreOp
= enums::SimdUnitStrideMaskStore;
static const OpClass SimdStridedLoadOp = enums::SimdStridedLoad;
static const OpClass SimdStridedStoreOp = enums::SimdStridedStore;
static const OpClass SimdIndexedLoadOp = enums::SimdIndexedLoad;
static const OpClass SimdIndexedStoreOp = enums::SimdIndexedStore;
static const OpClass SimdUnitStrideFaultOnlyFirstLoadOp
= enums::SimdUnitStrideFaultOnlyFirstLoad;
static const OpClass SimdWholeRegisterLoadOp
= enums::SimdWholeRegisterLoad;
static const OpClass SimdWholeRegisterStoreOp
= enums::SimdWholeRegisterStore;
static const OpClass IprAccessOp = enums::IprAccess;
static const OpClass InstPrefetchOp = enums::InstPrefetch;
static const OpClass VectorUnitStrideLoadOp = enums::VectorUnitStrideLoad;
static const OpClass VectorUnitStrideStoreOp = enums::VectorUnitStrideStore;
static const OpClass VectorUnitStrideMaskLoadOp
= enums::VectorUnitStrideMaskLoad;
static const OpClass VectorUnitStrideMaskStoreOp
= enums::VectorUnitStrideMaskStore;
static const OpClass VectorStridedLoadOp = enums::VectorStridedLoad;
static const OpClass VectorStridedStoreOp = enums::VectorStridedStore;
static const OpClass VectorIndexedLoadOp = enums::VectorIndexedLoad;
static const OpClass VectorIndexedStoreOp = enums::VectorIndexedStore;
static const OpClass VectorUnitStrideFaultOnlyFirstLoadOp
= enums::VectorUnitStrideFaultOnlyFirstLoad;
static const OpClass VectorWholeRegisterLoadOp
= enums::VectorWholeRegisterLoad;
static const OpClass VectorWholeRegisterStoreOp
= enums::VectorWholeRegisterStore;
static const OpClass VectorIntegerArithOp = enums::VectorIntegerArith;
static const OpClass VectorFloatArithOp = enums::VectorFloatArith;
static const OpClass VectorFloatConvertOp = enums::VectorFloatConvert;
static const OpClass VectorIntegerReduceOp = enums::VectorIntegerReduce;
static const OpClass VectorFloatReduceOp = enums::VectorFloatReduce;
static const OpClass VectorMiscOp = enums::VectorMisc;
static const OpClass VectorIntegerExtensionOp = enums::VectorIntegerExtension;
static const OpClass VectorUnitStrideSegmentedLoadOp = enums::VectorUnitStrideSegmentedLoad;
static const OpClass VectorConfigOp = enums::VectorConfig;
static const OpClass VectorUnitStrideSegmentedStoreOp
= enums::VectorUnitStrideSegmentedStore;
static const OpClass SimdUnitStrideSegmentedLoadOp = enums::SimdUnitStrideSegmentedLoad;
static const OpClass SimdUnitStrideSegmentedStoreOp
= enums::SimdUnitStrideSegmentedStore;
static const OpClass SimdExtOp = enums::SimdExt;
static const OpClass SimdFloatExtOp = enums::SimdFloatExt;
static const OpClass SimdConfigOp = enums::SimdConfig;
static const OpClass Num_OpClasses = enums::Num_OpClass;
} // namespace gem5

5
src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
View File

@@ -76,10 +76,6 @@ class U74MiscFU(MinorDefaultMiscFU):
pass
class U74VecFU(MinorDefaultVecFU):
pass
class U74FUPool(MinorFUPool):
funcUnits = [
U74IntFU(),
@@ -91,7 +87,6 @@ class U74FUPool(MinorFUPool):
U74MemReadFU(),
U74MemWriteFU(),
U74MiscFU(),
U74VecFU(),
]