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arch-arm: Group testTranslation and finalizeTranslation together

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They both make final checks to the VA->PA translation before
relinquishing control back to the translate client (usually
CPU code)

Change-Id: Ib0a9da25404248c22c6a240817d2f50f0913fdf7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-02-21 14:04:06 +00:00
parent 0c20eb3ec7
commit 89323c5112
2 changed files with 29 additions and 17 deletions
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40
src/arch/arm/mmu.cc
View File

@@ -199,6 +199,26 @@ MMU::invalidateMiscReg()
s2State.computeAddrTop.flush();
}
Fault
MMU::testAndFinalize(const RequestPtr &req,
ThreadContext *tc, Mode mode,
TlbEntry* te, CachedState &state) const
{
// If we don't have a valid tlb entry it means virtual memory
// is not enabled
auto domain = te ? te-> domain : TlbEntry::DomainType::NoAccess;
// Check for a tester generated address fault
Fault fault = testTranslation(req, mode, domain, state);
if (fault != NoFault) {
return fault;
} else {
// Now that we checked no fault has been generated in the
// translation process, we can finalize the physical address
return finalizePhysical(req, tc, mode);
}
}
Fault
MMU::finalizePhysical(const RequestPtr &req,
ThreadContext *tc, Mode mode) const
@@ -848,12 +868,7 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
state.isStage2);
setAttr(temp_te.attributes);
Fault fault = testTranslation(req, mode, TlbEntry::DomainType::NoAccess, state);
if (fault == NoFault) {
return finalizePhysical(req, tc, mode);
} else {
return fault;
}
return testAndFinalize(req, tc, mode, nullptr, state);
}
Fault
@@ -914,18 +929,11 @@ MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode,
tranMethod);
}
// Check for a trickbox generated address fault
if (fault == NoFault)
fault = testTranslation(req, mode, te->domain, state);
fault = testAndFinalize(req, tc, mode, te, state);
}
if (fault == NoFault) {
// Don't try to finalize a physical address unless the
// translation has completed (i.e., there is a table entry).
return te ? finalizePhysical(req, tc, mode) : NoFault;
} else {
return fault;
}
return fault;
}
Fault
@@ -1565,7 +1573,7 @@ MMU::setTestInterface(SimObject *_ti)
Fault
MMU::testTranslation(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain, CachedState &state)
TlbEntry::DomainType domain, CachedState &state) const
{
if (!test || !req->hasSize() || req->getSize() == 0 ||
req->isCacheMaintenance()) {

6
src/arch/arm/mmu.hh
View File

@@ -460,7 +460,7 @@ class MMU : public BaseMMU
void setTestInterface(SimObject *ti);
Fault testTranslation(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain, CachedState &state);
TlbEntry::DomainType domain, CachedState &state) const;
protected:
bool checkWalkCache() const;
@@ -471,6 +471,10 @@ class MMU : public BaseMMU
ThreadContext *tc, ArmTranslationType tran_type,
bool stage2);
Fault testAndFinalize(const RequestPtr &req,
ThreadContext *tc, Mode mode,
TlbEntry *te, CachedState &state) const;
protected:
ContextID miscRegContext;