Mrinmoy Ghosh 7e104a1af2 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

..

cache

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

MESI: Add queues for stalled requests

2012-02-10 11:05:24 -06:00

ruby

Ruby: Remove isTagPresent() calls from Sequencer.cc

2012-02-10 11:29:02 -06:00

slicc

Ruby: Add infrastructure for recording cache contents

2012-01-11 13:29:15 -06:00

bridge.cc

MEM: Make the bus bridge unidirectional and fixed address range

2012-01-17 12:55:09 -06:00

bridge.hh

MEM: Make the bus bridge unidirectional and fixed address range

2012-01-17 12:55:09 -06:00

Bridge.py

MEM: Make the bus bridge unidirectional and fixed address range

2012-01-17 12:55:09 -06:00

bus.cc

MEM: Remove onRetryList from BusPort and rely on retryList

2012-02-09 13:06:27 -05:00

bus.hh

MEM: Remove onRetryList from BusPort and rely on retryList

2012-02-09 13:06:27 -05:00

Bus.py

bus: clean up default responder code.

2010-08-17 05:06:21 -07:00

dram.cc

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

dram.hh

stats: Fix all stats usages to deal with template fixes

2009-03-05 19:09:53 -08:00

fs_translating_port_proxy.cc

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

fs_translating_port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

mem_object.cc

MEM: Remove Port removeConn and MemObject deletePortRefs

2012-01-17 12:55:09 -06:00

mem_object.hh

MEM: Remove Port removeConn and MemObject deletePortRefs

2012-01-17 12:55:09 -06:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

mport.hh

Create a message port for sending messages as apposed to reading/writing a memory range.

2008-10-12 12:08:51 -07:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet.cc

MemCmd: Add a command for invalidation requests to LSQ

2012-01-23 11:07:11 -06:00

packet.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

page_table.cc

Another merge with the main repository.

2012-01-07 02:16:37 -08:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

Merge with the main repo.

2012-01-28 07:24:01 -08:00

physical.hh

Mem: Add simple bandwidth stats to PhysicalMemory

2012-01-25 17:18:25 +00:00

PhysicalMemory.py

Make default PhysicalMemory latency slightly more realistic.

2008-08-03 18:13:29 -04:00

port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

port.cc

MEM: Remove Port removeConn and MemObject deletePortRefs

2012-01-17 12:55:09 -06:00

port.hh

MEM: Separate queries for snooping and address ranges

2012-01-17 12:55:09 -06:00

request.hh

Mem: Allow ASID to be set after request is created.

2011-09-13 12:06:13 -05:00

SConscript

Merge with the main repo.

2012-01-28 07:24:01 -08:00

se_translating_port_proxy.cc

Merge with the main repo.

2012-01-28 07:24:01 -08:00

se_translating_port_proxy.hh

MEM: Add port proxies instead of non-structural ports

2012-01-17 12:55:08 -06:00

tport.cc

MEM: Simplify ports by removing EventManager

2012-01-17 12:55:09 -06:00

tport.hh

MEM: Separate queries for snooping and address ranges

2012-01-17 12:55:09 -06:00