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7bcef5c048cf037407e697bd7382ac3bcdde9bba
gem5/src/mem
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Gabe Black 7bcef5c048 misc: Fix a few accidental transitive includes. 
Some files depend on definitions from files that they weren't including
themselves. They were working accidentally by getting those definitions
transitively through other, unrelated headers.

Change-Id: I50c919a4eb6c4484d4ee6b7f4fe02f075132964d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36282
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-21 22:56:14 +00:00
..
cache
misc: Fix a few accidental transitive includes.
2020-10-21 22:56:14 +00:00
probes
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
protocol
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
qos
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ruby
gpu-compute,mem-ruby: Properly create/handle WriteCompletePkts
2020-10-15 17:52:51 +00:00
slicc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
abstract_mem.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
abstract_mem.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
AbstractMemory.py
mem: Support initializing a memory with an image file.
2020-04-16 23:43:08 +00:00
addr_mapper.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
addr_mapper.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
AddrMapper.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
backdoor.hh
misc: Rename CallbackQueue2 to CallbackQueue.
2020-08-18 23:21:30 +00:00
bridge.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
bridge.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
Bridge.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
coherent_xbar.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
coherent_xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
comm_monitor.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
comm_monitor.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
CommMonitor.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
DRAMInterface.py
mem: Clean up Memory Controller
2020-09-08 16:38:47 +00:00
drampower.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
drampower.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim2_wrapper.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
dramsim2_wrapper.hh
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
dramsim2.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim2.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim3_wrapper.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
dramsim3_wrapper.hh
mem,ext: Integrating DRAMSim3 with gem5
2020-09-02 15:51:00 +00:00
dramsim3.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
dramsim3.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
DRAMsim3.py
mem,ext: Integrating DRAMSim3 with gem5
2020-09-02 15:51:00 +00:00
DRAMSim2.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
external_master.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
external_master.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
external_slave.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
external_slave.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ExternalMaster.py
mem: Update port terminology
2020-08-26 16:48:13 +00:00
ExternalSlave.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
hmc_controller.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
hmc_controller.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
HMCController.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
htm.cc
arch, mem: Initial Hardware Transactional Memory implementation
2020-09-02 08:30:11 +00:00
htm.hh
arch, mem: Initial Hardware Transactional Memory implementation
2020-09-02 08:30:11 +00:00
mem_checker_monitor.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_checker_monitor.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_checker.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_checker.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_ctrl.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_ctrl.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_delay.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_delay.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_interface.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_interface.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_object.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
mem_requestor.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemChecker.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemCtrl.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemDelay.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
MemInterface.py
mem: Clean up Memory Controller
2020-09-08 16:38:47 +00:00
MemObject.py
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
multi_level_page_table.hh
configs,arch,sim: Move fixFuncEventAddr into the Workload class.
2020-04-22 00:22:28 +00:00
noncoherent_xbar.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
noncoherent_xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
NVMInterface.py
mem: Clean up Memory Controller
2020-09-08 16:38:47 +00:00
packet_access.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
packet_queue.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
packet_queue.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
packet.cc
mem: Add HTM fields to the Packet object
2020-09-08 09:13:30 +00:00
packet.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
page_table.cc
misc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 21:52:59 +00:00
page_table.hh
misc: Fix a few accidental transitive includes.
2020-10-21 22:56:14 +00:00
physical.cc
mem: Optionally share the backing store
2020-07-08 17:42:25 +00:00
physical.hh
mem: Optionally share the backing store
2020-07-08 17:42:25 +00:00
port_proxy.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
port_proxy.hh
mem: Update port terminology
2020-08-26 16:48:13 +00:00
port.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
port.hh
base,mem: Use the standard [[deprecated]] attribute.
2020-09-28 21:52:41 +00:00
qport.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
request.hh
cpu: Never use a empty byteEnable
2020-09-30 14:16:31 +00:00
SConscript
mem: Clean up Memory Controller
2020-09-08 16:38:47 +00:00
se_translating_port_proxy.cc
mem: fixupAddr should not panic if it fails.
2020-06-18 03:58:48 +00:00
se_translating_port_proxy.hh
mem: Default the SE translating port proxy alloc method to NextPage.
2020-06-09 10:02:26 +00:00
serial_link.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
serial_link.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SerialLink.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
simple_mem.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
simple_mem.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SimpleMemory.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
snoop_filter.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
snoop_filter.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
stack_dist_calc.cc
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
stack_dist_calc.hh
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
token_port.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
token_port.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tport.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
tport.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
translating_port_proxy.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
translating_port_proxy.hh
mem: Add a Request::Flags parameter to the translating port proxies.
2020-03-19 07:21:13 +00:00
xbar.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
xbar.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
XBar.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00