Giacomo Travaglini 330a5f7bad misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB ...

With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-10-21 09:33:39 +00:00

..

boot

configs: Remove old boot files

2020-05-08 17:14:03 +00:00

common

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

dist

config: Delete authors lists from config files.

2020-02-17 10:06:07 +00:00

dram

sim: Create a Workload object for SE mode.

2020-09-20 07:26:22 +00:00

example

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

learning_gem5

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

network

mem-garnet: Upgrade garnet version to 3.0

2020-09-11 05:38:09 +00:00

nvm

mem: Clean up Memory Controller

2020-09-08 16:38:47 +00:00

ruby

configs: Make GPU_VIPER config python3 friendly

2020-10-17 00:43:43 +00:00

splash2

configs,tests: Update configs to use compatible SE workloads.

2020-10-13 04:59:04 +00:00

topologies

configs: Updates for python3

2020-05-18 20:10:35 +00:00