Gabe Black 29bac1c422 riscv: Convert RISCV to use local reg index storage. ...

This was mostly straightforward, except that the micro and macro op
classes need to be seperated for AMO classes so that the reg_idx_arr_decl
will have the right sizes.

Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36881
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-12-06 23:09:00 +00:00

..

arm

arch-arm: add official names to all PMU events

2020-11-26 16:25:10 +00:00

gcn3

arch-gcn3: Explicitly sign-extend simm16

2020-11-17 17:08:24 +00:00

generic

arch: Move many of the generic files outside an NULL guard.

2020-10-29 20:23:35 +00:00

isa_parser

arch: Add some format strings to the parser for reg indexes.

2020-11-19 02:52:05 +00:00

mips

mips: Convert MIPS to use local register index storage.

2020-11-24 06:25:23 +00:00

null

base, sim, mem, arch: Remove the dummy CPU in NULL

2020-09-14 08:52:40 +00:00

power

power: Convert POWER to use local reg index storage.

2020-11-28 02:05:38 +00:00

riscv

riscv: Convert RISCV to use local reg index storage.

2020-12-06 23:09:00 +00:00

sparc

sparc: Convert SPARC to use local register index storage.

2020-11-24 06:25:14 +00:00

x86

x86: Let the pseudoInst dispatch function handle the return value.

2020-12-02 23:02:55 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch,sim: Handle KVM SE page faults with workload events.

2020-10-29 20:23:26 +00:00