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gem5/src/arch/generic
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Gabe Black 6c454ee53b arch: Move many of the generic files outside an NULL guard. 
These files can be compiled successfully even if the ISA is the NULL
ISA.

Change-Id: I67133ea674f678f33b0aa1ef55af719f2869241d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34169
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-29 20:23:35 +00:00
..
freebsd
sim: Retrofit the VPtr type.
2020-07-04 17:53:54 +00:00
linux
arch: Remove unused variable pcbb from ThreadInfo
2020-09-01 06:25:28 +00:00
BaseInterrupts.py
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
BaseISA.py
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
BaseMMU.py
misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
2020-10-21 09:33:39 +00:00
BaseTLB.py
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
debugfaults.hh
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
decode_cache.cc
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
decode_cache.hh
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
decoder.cc
cpu,arch: Delegate fetching ROM microops to the decoder.
2020-08-25 12:41:20 +00:00
decoder.hh
cpu,arch: Delegate fetching ROM microops to the decoder.
2020-08-25 12:41:20 +00:00
htm.cc
arch, mem: Initial Hardware Transactional Memory implementation
2020-09-02 08:30:11 +00:00
htm.hh
arch: Add a virtual destructor to BaseHTMCheckpoint.
2020-09-09 07:08:53 +00:00
interrupts.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
isa.hh
arch,cpu: Add a setThreadContext method to the ISA class.
2020-06-12 05:41:41 +00:00
ISACommon.py
arch: Delete authors lists from generic arch files.
2020-02-18 03:34:56 +00:00
locked_mem.hh
arch: Don't add contents to the TheISA namespace in arch/generic.
2020-08-20 01:36:24 +00:00
memhelpers.hh
arch: Add raw read/writeMem helpers
2020-09-30 08:50:39 +00:00
mmu.cc
arch: Add generic BaseMMU
2020-10-07 10:48:14 +00:00
mmu.hh
arch: Use getTlb in BaseMMU to reduce boilerplate
2020-10-21 09:47:57 +00:00
SConscript
arch: Move many of the generic files outside an NULL guard.
2020-10-29 20:23:35 +00:00
tlb.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
traits.hh
arch, arch-arm: Use BaseISA in RenameMode interface
2020-02-19 14:54:24 +00:00
types.hh
arch: Add uReset helper to UPCState
2020-09-02 08:30:11 +00:00
vec_pred_reg.hh
misc: Replace enable_if<>::type with enable_if_t<>.
2020-10-23 12:59:59 +00:00
vec_reg.hh
misc: Replace enable_if<>::type with enable_if_t<>.
2020-10-23 12:59:59 +00:00