Luming Wang 73267e67c4 arch-riscv: reduced lr/sc implementation
In gem5::RiscvISA::ISA, handleLocked* functions maintain an address
stack(i.e. locked_addrs) to check whether each SC matches the most
recent LR. However, there are some problems with this implementation.

First, the elements in the stack may only be popped when the
handleLockedSnoop function is invoked. In other cases, the elements
in the stack will not be popped even if the SC and LR match. This
makes the `locked_addrs` get bigger and bigger as gem5 runs.

Second, LR/SC does not always match. For example, in Linux's __cmpxchg[1],
after executing LR, if the value read is not equal to the old value,
the subsequent SC is skipped. For gem5's current implementation, this
would cause the address to be pushed into `locked_addrs` every time
__cmpxchg is failed. But these addresses are never popped. This also
makes the `locked_addrs` get bigger and bigger.

Third, existing emulator implementations (spike, qemu) do not use the
stack, but only record the last address accessed by LR. Afterward,
when executing SC, these implementations determine whether the address
accessed by SC is the same as the one recorded.

This patch modifies gem5's handleLocked* function by referring to
other existing RISC-V implementations. It eliminates `locked_addrs`
and simplifies the related code. Thus, it fixes the "memory leak"-like
error that can occur on `locked_addrs` when executing LR/SC.

Related links:
[1] Linux's cmpxchg implementation for RISC-V:
  + https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/cmpxchg.h
[2] spike lr/sc implementation:
  + https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/sc_d.h
  + https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/lr_d.h
  + https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/mmu.h
[3] rocket lr/sc implementation:
  + https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/NBDcache.scala
[4] QEMU lr/sc implementation:
  + https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/insn_trans/trans_rva.c.inc

Change-Id: Ic79444cace62e39b7fe9e01f665cb13e4d990d0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55663
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-21 13:41:23 +00:00
2022-01-20 01:16:02 +00:00
2022-01-20 15:26:58 +00:00
2020-10-22 01:01:46 +00:00
2020-07-14 18:41:37 +00:00
2017-03-01 11:58:37 +00:00
2021-09-23 23:14:55 +00:00

This is the gem5 simulator.

The main website can be found at http://www.gem5.org

A good starting point is http://www.gem5.org/about, and for
more information about building the simulator and getting started
please see http://www.gem5.org/documentation and
http://www.gem5.org/documentation/learning_gem5/introduction.

To build gem5, you will need the following software: g++ or clang,
Python (gem5 links in the Python interpreter), SCons, zlib, m4, and lastly
protobuf if you want trace capture and playback support. Please see
http://www.gem5.org/documentation/general_docs/building for more details
concerning the minimum versions of these tools.

Once you have all dependencies resolved, type 'scons
build/<CONFIG>/gem5.opt' where CONFIG is one of the options in build_opts like
ARM, NULL, MIPS, POWER, SPARC, X86, Garnet_standalone, etc. This will build an
optimized version of the gem5 binary (gem5.opt) with the the specified
configuration. See http://www.gem5.org/documentation/general_docs/building for
more details and options.

The main source tree includes these subdirectories:
   - build_opts: pre-made default configurations for gem5
   - build_tools: tools used internally by gem5's build process.
   - configs: example simulation configuration scripts
   - ext: less-common external packages needed to build gem5
   - include: include files for use in other programs
   - site_scons: modular components of the build system
   - src: source code of the gem5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you may need compiled system firmware, kernel
binaries and one or more disk images, depending on gem5's configuration and
what type of workload you're trying to run. Many of those resources can be
downloaded from http://resources.gem5.org, and/or from the git repository here:
https://gem5.googlesource.com/public/gem5-resources/

If you have questions, please send mail to gem5-users@gem5.org

Enjoy using gem5 and please share your modifications and extensions.
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