Sandipan Das 706f58c4e5 arch-power: Add byte order attribute for PC state ...

This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.

Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40940
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-07-04 18:18:53 +00:00

..

amdgpu

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

arm

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

gcn3

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

generic

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa_parser

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

mips

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

null

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

power

arch-power: Add byte order attribute for PC state

2021-07-04 18:18:53 +00:00

riscv

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

sparc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

x86

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

micro_asm_test.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

micro_asm.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

SConscript

arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh.

2021-05-28 23:41:03 +00:00

SConsopts

scons: Pull domain specific build setup out of SConstruct.

2021-04-03 01:18:17 +00:00