arch-power: Add byte order attribute for PC state

This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.

Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40940
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/power/decoder.hh

@@ -68,7 +68,7 @@ class Decoder : public InstDecoder
     void
     moreBytes(const PCState &pc, Addr fetchPC)
     {
-        emi = betoh(emi);
+        emi = gtoh(emi, pc.byteOrder());
         instDone = true;
     }
 

src/arch/power/pcstate.hh

@@ -30,6 +30,8 @@
 #define __ARCH_POWER_PCSTATE_HH__
 
 #include "arch/generic/types.hh"
+#include "arch/power/types.hh"
+#include "enums/ByteOrder.hh"
 
 namespace gem5
 {
@@ -37,7 +39,40 @@ namespace gem5
 namespace PowerISA
 {
 
-typedef GenericISA::SimplePCState<4> PCState;
+class PCState : public GenericISA::SimplePCState<4>
+{
+  private:
+    typedef GenericISA::SimplePCState<4> Base;
+    ByteOrder guestByteOrder = ByteOrder::big;
+
+  public:
+    PCState()
+    {}
+
+    void
+    set(Addr val)
+    {
+        Base::set(val);
+        npc(val + 4);
+    }
+
+    PCState(Addr val)
+    {
+        set(val);
+    }
+
+    ByteOrder
+    byteOrder() const
+    {
+        return guestByteOrder;
+    }
+
+    void
+    byteOrder(ByteOrder order)
+    {
+        guestByteOrder = order;
+    }
+};
 
 } // namespace PowerISA
 } // namespace gem5