derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6d27a3bb502ac27b2837260cff65b294c8d3a8b8
gem5/src/cpu/o3
History
Gabe Black 6d27a3bb50 cpu,arch: Turn the read|set*Operand methods into get/setRegOperand. 
This simplifies and generalizes the ExecContext interface significantly.
This does *not* change the "Writeable" accessors for the vec and pred
registers, and it also ignores MiscRegs which have some different
semantics.

Change-Id: I8cb80da890fc8915f03be04e136662a257d06946
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49114
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-19 20:23:51 +00:00
..
probe
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
BaseO3Checker.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
BaseO3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm.hh
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
commit.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
commit.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
cpu.cc
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
cpu.hh
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
decode.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decode.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
dep_graph.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst_ptr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst.cc
arch,cpu: Stop using and remove ThreadContext::instAddr.
2021-11-30 23:30:06 +00:00
dyn_inst.hh
cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
2022-02-19 20:23:51 +00:00
fetch.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
free_list.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
free_list.hh
cpu-o3: Remove unnecessary this->s from DynInst and SimpleFreeList.
2021-11-05 22:57:29 +00:00
fu_pool.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fu_pool.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnitConfig.py
cpu: Delete authors lists from the cpu directory.
2020-02-17 21:51:23 +00:00
FUPool.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
iew.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
iew.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
inst_queue.cc
cpu: rename RegClass::size to RegClass::numRegs.
2022-02-04 12:11:59 +00:00
inst_queue.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
limits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq_unit.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
lsq_unit.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
lsq.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
lsq.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
mem_dep_unit.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
mem_dep_unit.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
regfile.cc
cpu: Store raw byte vectors for register files.
2022-02-07 09:58:38 +00:00
regfile.hh
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
rename_map.cc
cpu: rename RegClass::size to RegClass::numRegs.
2022-02-04 12:11:59 +00:00
rename_map.hh
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
rename.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rename.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
SConscript
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
scoreboard.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
scoreboard.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.cc
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
thread_context.hh
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
thread_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00