Giacomo Travaglini 6b6ac525f7 arch-arm: PSTATE.PAN changes should inval cached regs in TLB ...

Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-09-19 10:54:14 +00:00

..

alpha

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

arm

arch-arm: PSTATE.PAN changes should inval cached regs in TLB

2019-09-19 10:54:14 +00:00

generic

arch, x86: Rework the debug faults and microops.

2019-09-18 06:26:35 +00:00

hsail

arch-hsail: changed gen.py shebang from python(3) to python2.7

2019-03-11 22:13:24 +00:00

mips

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

null

cpu, arch: Replace the CCReg type with RegVal.

2019-02-01 01:22:19 +00:00

power

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

riscv

arch-riscv: fix GDB register cache

2019-08-23 23:13:40 +00:00

sparc

sparc: Fix a warning/error in tlb.cc.

2019-09-13 00:55:25 +00:00

x86

arch, x86: Rework the debug faults and microops.

2019-09-18 06:26:35 +00:00

isa_parser.py

arch: Add include guards to auto-gen. decode header

2019-05-30 15:56:17 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the mt.hh switching header.

2019-04-30 16:27:17 +00:00