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arch-arm: PSTATE.PAN changes should inval cached regs in TLB

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Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-09-05 10:52:47 +01:00
parent ee00675d24
commit 6b6ac525f7
1 changed files with 4 additions and 0 deletions
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4
src/arch/arm/isa.cc
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@@ -791,6 +791,10 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
getDTBPtr(tc)->invalidateMiscReg();
}
if (cpsr.pan != old_cpsr.pan) {
getDTBPtr(tc)->invalidateMiscReg();
}
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
PCState pc = tc->pcState();