Mahyar Samani 6a2283e575 misc: Adding multi-channel memory to components library ...

This change adds source code for multi-channel memory in the
components library.

Change-Id: I52b5462939d4d2d1657c85394bd83afdb509a0b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51287
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-10-29 06:01:11 +00:00

..

arch

arch-arm,cpu: Replace rename modes with split reg/elem register files.

2021-10-28 06:00:07 +00:00

base

base,arch-arm: Replace Stats namespace with statistics.

2021-10-13 20:28:52 +00:00

cpu

arch-arm,cpu: Replace rename modes with split reg/elem register files.

2021-10-28 06:00:07 +00:00

dev

dev: Separate generateDeviceTree into a RiscvUart8250 SimObject.

2021-10-28 20:27:16 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

misc: Remove include of arch/page_size.hh, and fix up includes.

2021-10-22 21:43:02 +00:00

kern

sim-se, kern: Add flags parameter to unlinkat

2021-10-14 08:52:39 +00:00

learning_gem5

misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].

2021-07-29 10:17:51 +00:00

mem

mem-ruby: Don't conditionalize setting RubySequencer's pio_response_port

2021-10-29 02:20:36 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

misc: Adding multi-channel memory to components library

2021-10-29 06:01:11 +00:00

sim

misc: Remove include of arch/page_size.hh, and fix up includes.

2021-10-22 21:43:02 +00:00

systemc

systemc: Stop including mem/port.hh from the systemc headers.

2021-08-28 04:18:12 +00:00

Doxyfile

misc: Update the version to v21.1.0.2

2021-09-22 18:37:48 +00:00

SConscript

scons: Fix linker flags for prof/perf builds.

2021-10-26 03:32:10 +00:00