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mem-ruby: Don't conditionalize setting RubySequencer's pio_response_port

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This was conditioned on the TARGET_ISA being x86 because the code it
replaced was, and that was because the x86 interrupts object had an
extra port that didn't appear for other ISAs. This inconsistency is not
present on either side of this connection, and so we don't need it to be
conditional.

We do, however, need to ensure that the port sends a range change even
if it doesn't have any ranges to send, to satisfy the bookkeeping of the
bus on the other side of the connection. We do that in init, like leaf
devices do.

Change-Id: Idec6f6c5e2cf78b113fb238d0edd2c63d6cd2c23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52109
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-27 02:14:44 -07:00
parent 996f0ce168
commit c02abad641
2 changed files with 4 additions and 3 deletions
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3
src/mem/ruby/system/RubyPort.cc
View File

@@ -95,6 +95,9 @@ RubyPort::init()
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
for (const auto &response_port : response_ports)
response_port->sendRangeChange();
if (gotAddrRanges == 0 && FullSystem) {
pioResponsePort.sendRangeChange();
}
}
Port &

4
src/mem/ruby/system/Sequencer.py
View File

@@ -122,11 +122,9 @@ class RubySequencer(RubyPort):
do not go though the SLICC protocol so the iobus must be connected to
the sequencer directly.
"""
import m5.defines
self.pio_request_port = piobus.cpu_side_ports
self.mem_request_port = piobus.cpu_side_ports
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
self.pio_response_port = piobus.mem_side_ports
self.pio_response_port = piobus.mem_side_ports
class RubyHTMSequencer(RubySequencer):
type = 'RubyHTMSequencer'