diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ff02fde7cd..37c34c5f75 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -95,6 +95,9 @@ RubyPort::init()
     m_mandatory_q_ptr = m_controller->getMandatoryQueue();
     for (const auto &response_port : response_ports)
         response_port->sendRangeChange();
+    if (gotAddrRanges == 0 && FullSystem) {
+        pioResponsePort.sendRangeChange();
+    }
 }
 
 Port &
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 50e871849e..703c533dcc 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -122,11 +122,9 @@ class RubySequencer(RubyPort):
         do not go though the SLICC protocol so the iobus must be connected to
         the sequencer directly.
         """
-        import m5.defines
         self.pio_request_port = piobus.cpu_side_ports
         self.mem_request_port = piobus.cpu_side_ports
-        if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-            self.pio_response_port = piobus.mem_side_ports
+        self.pio_response_port = piobus.mem_side_ports
 
 class RubyHTMSequencer(RubySequencer):
     type = 'RubyHTMSequencer'