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66d3f7c03882deba66f0328339842b9199a65387
gem5/src/cpu
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studyztp 66d3f7c038 cpu: add GlobalInstTracker and LocalInstTracker 
The GlobalInstTracker manages the global instruction counter and
responsible for triggering an exit event when the global instruction
counter reaches the defined threshold.

The LocalInstTracker listens to one core's retiredInsts probe point
and updates the GlobalInstTracker every time there is an instruction
committed.

The purpose of this instruction tracker is to raise an instruction
executed exit event with multi-core simulation.

Related discussion can be found:
https://github.com/gem5/gem5/issues/1087

Change-Id: Iab6fec57f14f28e590b035506282130ba8662706
2024-11-18 11:23:34 -08:00
..
checker
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
kvm
Revert "cpu-kvm: Support perf counters on hybrid host architectures" (#1127)
2024-05-21 08:14:10 -07:00
minor
misc: Do not share the random number generator across components (#1534)
2024-11-18 01:37:12 -08:00
o3
misc: Do not share the random number generator across components (#1534)
2024-11-18 01:37:12 -08:00
pred
misc: Do not share the random number generator across components (#1534)
2024-11-18 01:37:12 -08:00
probes
cpu: add GlobalInstTracker and LocalInstTracker
2024-11-18 11:23:34 -08:00
simple
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
testers
misc: Do not share the random number generator across components (#1534)
2024-11-18 01:37:12 -08:00
trace
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
activity.cc
misc: Fix 'unused variable' clang errors with gem5.fast
2023-05-08 22:54:06 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
cpu: fix simInsts and simOps not resetting (#1615)
2024-10-09 19:49:43 -07:00
base.hh
cpu: fix simInsts and simOps not resetting (#1615)
2024-10-09 19:49:43 -07:00
BaseCPU.py
cpu: Add cpuIdlePins to indicate the threadContext of CPU is idle (#1285)
2024-07-10 10:36:37 +01:00
capstone.cc
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
capstone.hh
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
Capstone.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
CheckerCPU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
cluster.hh
cpu: Formalize a CPU cluster class in the gem5 standard library
2023-01-13 12:07:51 +00:00
CpuCluster.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
CPUTracers.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
decode_cache.hh
cpu: Remove the DecodeCache namespace
2023-01-17 09:16:20 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
exec_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
exetrace.cc
arch, cpu: Add generic getValidAddr to correct exetrace symbol table (#1758)
2024-11-08 13:33:53 +00:00
exetrace.hh
arch,cpu,sim: Add mechanism to partially print vector regs (#1234)
2024-06-17 14:05:47 -07:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
cpu: This commit updates cpu FUs according to new Simd types
2024-03-25 19:01:47 +01:00
inst_pb_trace.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inst_pb_trace.hh
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inst_res.hh
arch,cpu,sim: Add mechanism to partially print vector regs (#1234)
2024-06-17 14:05:47 -07:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
inteltrace.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inteltrace.hh
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
Kconfig
arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)
2023-12-03 13:22:11 -08:00
nativetrace.cc
cpu: Pass a reference of the parent tracer to the ExeTracerRecord
2023-10-20 09:27:50 +01:00
nativetrace.hh
cpu: Pass a reference of the parent tracer to the ExeTracerRecord
2023-10-20 09:27:50 +01:00
nop_static_inst.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
cpu: This commit updates cpu FUs according to new Simd types
2024-03-25 19:01:47 +01:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
base: Add encapsulation to the loader::Symbol class
2023-12-01 22:00:26 +00:00
profile.hh
base: Remove the Loader namespace
2023-01-17 09:16:20 +00:00
reg_class.cc
arch,cpu,sim: Add mechanism to partially print vector regs (#1234)
2024-06-17 14:05:47 -07:00
reg_class.hh
cpu: Fix std::min type mismatch in reg_class.hh (#1266)
2024-06-20 13:02:08 -07:00
regfile.hh
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
SConscript
arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)
2023-12-03 13:22:11 -08:00
SConsopts
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
simple_thread.cc
cpu: Revert "Don't change to suspend if the thread status is halted" (#1225)
2024-06-12 00:20:06 -07:00
simple_thread.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
static_inst.hh
cpu: Add IsInvalid flag to StaticInstFlags
2024-06-11 18:48:29 +00:00
StaticInstFlags.py
cpu: Add IsInvalid flag to StaticInstFlags
2024-06-11 18:48:29 +00:00
thread_context.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
thread_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
cpu: Merge TimingExprSrcReg and TimingExprReadIntReg.
2022-06-24 11:26:51 +00:00
timing_expr.hh
cpu: Merge TimingExprSrcReg and TimingExprReadIntReg.
2022-06-24 11:26:51 +00:00
TimingExpr.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
translation.hh
Revert "arch-x86: Fix TLB Assertion Error on CFLUSH" (#1196)
2024-06-04 10:26:53 -07:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00