Gabe Black 64171d4d14 cpu,arch: Attach a debug flag to each RegClass. ...

This can be used for DPRINTFs related to those registers using DPRINTFV.

Change-Id: I0fccb12b70fdb74e01022fe0d3d9c2f92425a5bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49696
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2022-02-24 00:10:17 +00:00

..

amdgpu

arch-vega: Fix global 64-bit calcAddr with SGPR base

2022-01-20 16:03:23 +00:00

arm

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

generic

cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.

2022-02-19 20:23:51 +00:00

isa_parser

cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.

2022-02-19 20:23:51 +00:00

mips

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

null

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

power

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

riscv

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

sparc

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

x86

cpu,arch: Attach a debug flag to each RegClass.

2022-02-24 00:10:17 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

scons: Work around a SCons bug in Glob.

2022-02-15 22:55:35 +00:00

SConscript

scons: Work around a SCons bug in Glob.

2022-02-15 22:55:35 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00