Gabe Black 5eb3e44f54 fastmodel: Add an ISA class which defers to IRIS. ...

This class is just to enable checkpointing of "ISA" state, aka the
MiscRegs.

Change-Id: I45315b8aaa09aaf6230f44665c13597400efd780
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29822
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-09-10 11:29:11 +00:00

..

arch

fastmodel: Add an ISA class which defers to IRIS.

2020-09-10 11:29:11 +00:00

base

base: Tag API methods in crc.hh

2020-09-08 16:32:38 +00:00

cpu

cpu-o3: convert rename to new style stats

2020-09-09 14:37:37 +00:00

dev

arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.

2020-09-08 23:57:56 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

misc: Use VPtr in hsa_driver.cc

2020-08-31 17:44:11 +00:00

kern

misc: Clean up usage of arch/isa_traits.hh.

2020-08-28 07:20:58 +00:00

learning_gem5

learning-gem5: convert simple cache to new style stats

2020-09-05 01:51:30 +00:00

mem

mem: Remove the unused nvm private member from NVMInterface::Rank.

2020-09-09 07:08:53 +00:00

proto

misc: Use the protobuf version to choose between ByteSize(Long).

2020-04-29 21:46:11 +00:00

python

base, sim: Make ByteOrder into a ScopedEnum accessible to Python

2020-09-08 16:24:00 +00:00

sim

sim: Expose the system's byte order as a param

2020-09-09 09:49:47 +00:00

systemc

systemc: Send response to TLM side if a packet does not need response

2020-08-27 00:15:26 +00:00

unittest

base: Make the Value stat's functor method accept lambdas.

2020-09-01 21:57:34 +00:00

Doxyfile

misc: Reverting version numbers

2020-07-03 20:59:44 -07:00

SConscript

scons: Simplify arch enum generation

2020-09-07 08:42:07 +00:00