sim: Expose the system's byte order as a param

There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.

Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

src/sim/System.py

@@ -48,6 +48,11 @@ from m5.objects.SimpleMemory import *
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
                                 'atomic_noncaching']
 
+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+    default_byte_order = 'big'
+else:
+    default_byte_order = 'little'
+
 class System(SimObject):
     type = 'System'
     cxx_header = "sim/system.hh"
@@ -84,6 +89,9 @@ class System(SimObject):
 
     cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
 
+    byte_order = Param.ByteOrder(default_byte_order,
+                                 "Default byte order of system components")
+
     redirect_paths = VectorParam.RedirectPath([], "Path redirections")
 
     exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "

src/sim/system.hh

@@ -386,11 +386,7 @@ class System : public SimObject, public PCEventScope
     ByteOrder
     getGuestByteOrder() const
     {
-#if THE_ISA != NULL_ISA
-        return TheISA::GuestByteOrder;
-#else
-        panic("The NULL ISA has no endianness.");
-#endif
+        return _params->byte_order;
     }
 
      /**