Daniel R. Carvalho 5a1414d782 arch: Remove a couple of deprecated namespaces ...

These namespaces have gone through the deprecation period
and can now be removed: X86Macroops, SMBios, RomLabels,
DeliveryMode, ConditionTests.

Change-Id: I6ff5e98319d92e27743a9fbeeab054497a2392e0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67375
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

2023-01-17 20:09:09 +00:00

..

amdgpu

arch-vega: Implement ds_write2st64_b64

2023-01-05 23:12:10 +00:00

arm

arch-arm, cpu: Implement instructions added by FEAT_SME

2023-01-17 10:09:56 +00:00

generic

misc: Remove the FreeBSD namespace

2023-01-17 09:16:20 +00:00

isa_parser

arch, arch-arm, cpu: Add matrix reg support to the ISA Parser

2023-01-17 10:09:56 +00:00

mips

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

riscv

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

sparc

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

x86

arch: Remove a couple of deprecated namespaces

2023-01-17 20:09:09 +00:00

micro_asm_test.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

micro_asm.py

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00