Gabe Black 47cda1d20b x86: Add a ld/st microop flag for marking an access uncacheable. ...

This percolates down to the memory request object which will have its
"UNCACHEABLE" flag set.

Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce
Reviewed-on: https://gem5-review.googlesource.com/9881
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

2018-05-02 23:25:09 +00:00

..

alpha

arch: alpha: Fix an 8 year old bug from the transition to pc objects.

2018-04-06 23:47:22 +00:00

arm

sim,cpu,mem,arch: Introduced MasterInfo data structure

2018-04-27 16:00:28 +00:00

generic

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

2018-03-27 10:57:54 +00:00

hsail

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

mips

arch: Fix all override related warnings.

2018-03-26 22:34:44 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

arch: Fix all override related warnings.

2018-03-26 22:34:44 +00:00

riscv

arch: cpu: Make the ExtMachInst type a template argument in InstMap.

2018-03-27 10:57:54 +00:00

sparc

sparc: Add some missing M5_FALLTHROUGHs and breaks.

2018-03-27 10:57:45 +00:00

x86

x86: Add a ld/st microop flag for marking an access uncacheable.

2018-05-02 23:25:09 +00:00

isa_parser.py

arch, arm: Fix implicit-fallthrough GCC warnings

2018-03-20 20:17:00 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "arch/tlb.hh" switching header.

2018-01-23 20:39:24 +00:00