arch: Fix all override related warnings.

Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-23 17:39:32 -07:00
parent 740619f5d3
commit cdf3cc2b95
66 changed files with 676 additions and 492 deletions
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -81,13 +81,14 @@ output header {{
        {
        }

-        AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const;
+        AlphaISA::PCState branchTarget(
+                const AlphaISA::PCState &branchPC) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -109,13 +110,13 @@ output header {{
        {
        }

-        AlphaISA::PCState branchTarget(ThreadContext *tc) const;
+        AlphaISA::PCState branchTarget(ThreadContext *tc) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -126,8 +126,8 @@ output header {{

        // This differs from the AlphaStaticInst version only in
        // printing suffixes for non-default rounding & trapping modes.
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

 }};
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -49,8 +49,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -232,11 +232,11 @@ output header {{
        /// dependence tag number (FP or int).
        void printReg(std::ostream &os, RegId reg) const;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;

        void
-        advancePC(AlphaISA::PCState &pcState) const
+        advancePC(AlphaISA::PCState &pcState) const override
        {
            pcState.advance();
        }
@@ -263,8 +263,8 @@ output decoder {{
    }

    std::string
-    AlphaStaticInst::generateDisassembly(Addr pc,
-                                         const SymbolTable *symtab) const
+    AlphaStaticInst::generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

@@ -304,7 +304,7 @@ def template BasicDeclare {{
        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -383,10 +383,10 @@ output header {{

        ~Nop() { }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };

    /// Helper function for decoding nops.  Substitute Nop object
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -51,8 +51,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -88,8 +88,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -129,9 +129,10 @@ def template LoadStoreDeclare {{
        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -48,10 +48,10 @@ output header {{
        {
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -49,8 +49,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -93,8 +93,8 @@ output header {{
        CallPalBase(const char *mnem, ExtMachInst _machInst,
                    OpClass __opClass);

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -157,8 +157,8 @@ output header {{
        /// Constructor
        HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass);

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -239,8 +239,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -53,10 +53,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -84,10 +84,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -163,10 +163,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -55,12 +55,14 @@ class BranchImm64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
    {}

-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Conditionally Branch to a target computed with an immediate
@@ -75,7 +77,8 @@ class BranchImmCond64 : public BranchImm64
        BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Branch to a target computed with a register
@@ -90,7 +93,8 @@ class BranchReg64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Ret instruction
@@ -102,7 +106,8 @@ class BranchRet64 : public BranchReg64
        BranchReg64(mnem, _machInst, __opClass, _op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Eret instruction
@@ -113,7 +118,8 @@ class BranchEret64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Branch to a target computed with an immediate and a register
@@ -129,12 +135,14 @@ class BranchImmReg64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
    {}

-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // Branch to a target computed with two immediates
@@ -153,12 +161,14 @@ class BranchImmImmReg64 : public ArmStaticInst
        imm1(_imm1), imm2(_imm2), op1(_op1)
    {}

-    ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+    ArmISA::PCState branchTarget(
+            const ArmISA::PCState &branchPC) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 }
--- a/src/arch/arm/insts/data64.hh
+++ b/src/arch/arm/insts/data64.hh
@@ -57,7 +57,8 @@ class DataXImmOp : public ArmStaticInst
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXImmOnlyOp : public ArmStaticInst
@@ -72,7 +73,8 @@ class DataXImmOnlyOp : public ArmStaticInst
        dest(_dest), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXSRegOp : public ArmStaticInst
@@ -90,7 +92,8 @@ class DataXSRegOp : public ArmStaticInst
        shiftAmt(_shiftAmt), shiftType(_shiftType)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXERegOp : public ArmStaticInst
@@ -108,7 +111,8 @@ class DataXERegOp : public ArmStaticInst
        extendType(_extendType), shiftAmt(_shiftAmt)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX1RegOp : public ArmStaticInst
@@ -121,7 +125,8 @@ class DataX1RegOp : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX1RegImmOp : public ArmStaticInst
@@ -136,7 +141,8 @@ class DataX1RegImmOp : public ArmStaticInst
        imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX1Reg2ImmOp : public ArmStaticInst
@@ -152,7 +158,8 @@ class DataX1Reg2ImmOp : public ArmStaticInst
        imm1(_imm1), imm2(_imm2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX2RegOp : public ArmStaticInst
@@ -166,7 +173,8 @@ class DataX2RegOp : public ArmStaticInst
        dest(_dest), op1(_op1), op2(_op2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX2RegImmOp : public ArmStaticInst
@@ -182,7 +190,8 @@ class DataX2RegImmOp : public ArmStaticInst
        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataX3RegOp : public ArmStaticInst
@@ -197,7 +206,8 @@ class DataX3RegOp : public ArmStaticInst
        dest(_dest), op1(_op1), op2(_op2), op3(_op3)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXCondCompImmOp : public ArmStaticInst
@@ -215,7 +225,8 @@ class DataXCondCompImmOp : public ArmStaticInst
        op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXCondCompRegOp : public ArmStaticInst
@@ -232,7 +243,8 @@ class DataXCondCompRegOp : public ArmStaticInst
        op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataXCondSelOp : public ArmStaticInst
@@ -248,7 +260,8 @@ class DataXCondSelOp : public ArmStaticInst
        dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 }
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -73,7 +73,7 @@ class MicroOp : public PredOp

  public:
    void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
    {
        if (flags[IsLastMicroop]) {
            pcState.uEnd();
@@ -94,7 +94,7 @@ class MicroOpX : public ArmStaticInst

  public:
    void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
    {
        if (flags[IsLastMicroop]) {
            pcState.uEnd();
@@ -263,7 +263,8 @@ class MicroSetPCCPSR : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -281,7 +282,8 @@ class MicroIntMov : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -300,7 +302,8 @@ class MicroIntImmOp : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MicroIntImmXOp : public MicroOpX
@@ -316,7 +319,8 @@ class MicroIntImmXOp : public MicroOpX
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -334,7 +338,8 @@ class MicroIntOp : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MicroIntRegXOp : public MicroOp
@@ -353,7 +358,8 @@ class MicroIntRegXOp : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -392,7 +398,8 @@ class MicroMemOp : public MicroIntImmOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MicroMemPairOp : public MicroOp
@@ -412,7 +419,8 @@ class MicroMemPairOp : public MicroOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -60,7 +60,8 @@ class Swap : public PredOp
          dest(_dest), op1(_op1), base(_base)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MightBeMicro : public PredOp
@@ -118,13 +119,14 @@ class RfeOp : public MightBeMicro
    }

    StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // The address is a base register plus an immediate.
@@ -158,13 +160,14 @@ class SrsOp : public MightBeMicro
    }

    StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class Memory : public MightBeMicro
@@ -198,7 +201,7 @@ class Memory : public MightBeMicro
    }

    StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -56,7 +56,8 @@ class SysDC64 : public ArmStaticInst
        : ArmStaticInst(mnem, _machInst, __opClass), base(_base),
          dest((IntRegIndex)miscReg), imm(_imm)
    {}
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MightBeMicro64 : public ArmStaticInst
@@ -113,7 +114,7 @@ class Memory64 : public MightBeMicro64
    }

    StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
@@ -136,7 +137,8 @@ class MemoryImm64 : public Memory64
        : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryDImm64 : public MemoryImm64
@@ -151,7 +153,8 @@ class MemoryDImm64 : public MemoryImm64
          dest2(_dest2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryDImmEx64 : public MemoryDImm64
@@ -166,7 +169,8 @@ class MemoryDImmEx64 : public MemoryDImm64
                     _base, _imm), result(_result)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryPreIndex64 : public MemoryImm64
@@ -178,7 +182,8 @@ class MemoryPreIndex64 : public MemoryImm64
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryPostIndex64 : public MemoryImm64
@@ -190,7 +195,8 @@ class MemoryPostIndex64 : public MemoryImm64
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryReg64 : public Memory64
@@ -208,7 +214,8 @@ class MemoryReg64 : public Memory64
          offset(_offset), type(_type), shiftAmt(_shiftAmt)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryRaw64 : public Memory64
@@ -219,7 +226,8 @@ class MemoryRaw64 : public Memory64
        : Memory64(mnem, _machInst, __opClass, _dest, _base)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryEx64 : public Memory64
@@ -233,7 +241,8 @@ class MemoryEx64 : public Memory64
        : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MemoryLiteral64 : public Memory64
@@ -246,7 +255,8 @@ class MemoryLiteral64 : public Memory64
        : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };
 }

--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -52,7 +52,8 @@ class MrsOp : public PredOp
        PredOp(mnem, _machInst, __opClass), dest(_dest)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MsrBase : public PredOp
@@ -78,7 +79,8 @@ class MsrImmOp : public MsrBase
        MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MsrRegOp : public MsrBase
@@ -91,7 +93,8 @@ class MsrRegOp : public MsrBase
        MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MrrcOp : public PredOp
@@ -109,7 +112,8 @@ class MrrcOp : public PredOp
        dest2(_dest2), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class McrrOp : public PredOp
@@ -127,7 +131,8 @@ class McrrOp : public PredOp
        dest(_dest), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class ImmOp : public PredOp
@@ -140,7 +145,8 @@ class ImmOp : public PredOp
        PredOp(mnem, _machInst, __opClass), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegImmOp : public PredOp
@@ -154,7 +160,8 @@ class RegImmOp : public PredOp
        PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegOp : public PredOp
@@ -168,7 +175,8 @@ class RegRegOp : public PredOp
        PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegImmRegOp : public PredOp
@@ -184,7 +192,8 @@ class RegImmRegOp : public PredOp
        dest(_dest), imm(_imm), op1(_op1)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegRegImmOp : public PredOp
@@ -202,7 +211,8 @@ class RegRegRegImmOp : public PredOp
        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegRegRegOp : public PredOp
@@ -220,7 +230,8 @@ class RegRegRegRegOp : public PredOp
        dest(_dest), op1(_op1), op2(_op2), op3(_op3)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegRegOp : public PredOp
@@ -236,7 +247,8 @@ class RegRegRegOp : public PredOp
        dest(_dest), op1(_op1), op2(_op2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegImmOp : public PredOp
@@ -253,7 +265,8 @@ class RegRegImmOp : public PredOp
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MiscRegRegImmOp : public PredOp
@@ -270,7 +283,8 @@ class MiscRegRegImmOp : public PredOp
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegMiscRegImmOp : public PredOp
@@ -287,7 +301,8 @@ class RegMiscRegImmOp : public PredOp
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegImmImmOp : public PredOp
@@ -303,7 +318,8 @@ class RegImmImmOp : public PredOp
        dest(_dest), imm1(_imm1), imm2(_imm2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegImmImmOp : public PredOp
@@ -321,7 +337,8 @@ class RegRegImmImmOp : public PredOp
        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegImmRegShiftOp : public PredOp
@@ -341,7 +358,8 @@ class RegImmRegShiftOp : public PredOp
        shiftAmt(_shiftAmt), shiftType(_shiftType)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class UnknownOp : public PredOp
@@ -352,7 +370,8 @@ class UnknownOp : public PredOp
        PredOp(mnem, _machInst, __opClass)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 #endif
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -52,7 +52,8 @@ class ImmOp64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegImmImmOp64 : public ArmStaticInst
@@ -70,7 +71,8 @@ class RegRegImmImmOp64 : public ArmStaticInst
        dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegRegRegImmOp64 : public ArmStaticInst
@@ -88,7 +90,8 @@ class RegRegRegImmOp64 : public ArmStaticInst
        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class UnknownOp64 : public ArmStaticInst
@@ -99,7 +102,8 @@ class UnknownOp64 : public ArmStaticInst
        ArmStaticInst(mnem, _machInst, __opClass)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class MiscRegRegImmOp64 : public ArmStaticInst
@@ -116,7 +120,8 @@ class MiscRegRegImmOp64 : public ArmStaticInst
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class RegMiscRegImmOp64 : public ArmStaticInst
@@ -133,7 +138,8 @@ class RegMiscRegImmOp64 : public ArmStaticInst
        dest(_dest), op1(_op1), imm(_imm)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 #endif
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -223,7 +223,8 @@ class PredImmOp : public PredOp
            rotated_carry = bits(rotated_imm, 31);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -243,7 +244,8 @@ class PredIntOp : public PredOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataImmOp : public PredOp
@@ -261,7 +263,8 @@ class DataImmOp : public PredOp
        dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataRegOp : public PredOp
@@ -279,7 +282,8 @@ class DataRegOp : public PredOp
        shiftAmt(_shiftAmt), shiftType(_shiftType)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class DataRegRegOp : public PredOp
@@ -296,7 +300,8 @@ class DataRegRegOp : public PredOp
        shiftType(_shiftType)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -327,19 +332,20 @@ class PredMacroOp : public PredOp
    }

    StaticInstPtr
-    fetchMicroop(MicroPC microPC) const
+    fetchMicroop(MicroPC microPC) const override
    {
        assert(microPC < numMicroops);
        return microOps[microPC];
    }

    Fault
-    execute(ExecContext *, Trace::InstRecord *) const
+    execute(ExecContext *, Trace::InstRecord *) const override
    {
        panic("Execute method called when it shouldn't!");
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -56,9 +56,11 @@ class DecoderFaultInst : public ArmStaticInst
  public:
    DecoderFaultInst(ExtMachInst _machInst);

-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -80,10 +82,11 @@ class FailUnimplemented : public ArmStaticInst
    FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
                      const std::string& _fullMnemonic);

-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;

-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -109,10 +112,11 @@ class WarnUnimplemented : public ArmStaticInst
    WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
                      const std::string& _fullMnemonic);

-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;

-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -131,10 +135,11 @@ class McrMrcMiscInst : public ArmStaticInst
    McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
                   uint64_t _iss, MiscRegIndex _miscReg);

-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;

-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

 };

@@ -148,10 +153,11 @@ class McrMrcImplDefined : public McrMrcMiscInst
    McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
                      uint64_t _iss, MiscRegIndex _miscReg);

-    Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+    Fault execute(ExecContext *xc,
+                  Trace::InstRecord *traceData) const override;

-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

 };

--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -188,12 +188,13 @@ class ArmStaticInst : public StaticInst
                       uint64_t imm) const;

    void
-    advancePC(PCState &pcState) const
+    advancePC(PCState &pcState) const override
    {
        pcState.advance();
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

    static inline uint32_t
    cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -890,7 +890,8 @@ class FpCondCompRegOp : public FpOp
        op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpCondSelOp : public FpOp
@@ -906,7 +907,8 @@ class FpCondSelOp : public FpOp
        dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegOp : public FpOp
@@ -923,7 +925,8 @@ class FpRegRegOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegImmOp : public FpOp
@@ -940,7 +943,8 @@ class FpRegImmOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegImmOp : public FpOp
@@ -958,7 +962,8 @@ class FpRegRegImmOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegRegOp : public FpOp
@@ -976,7 +981,8 @@ class FpRegRegRegOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegRegCondOp : public FpOp
@@ -997,7 +1003,8 @@ class FpRegRegRegCondOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegRegRegOp : public FpOp
@@ -1017,7 +1024,8 @@ class FpRegRegRegRegOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class FpRegRegRegImmOp : public FpOp
@@ -1038,7 +1046,8 @@ class FpRegRegRegImmOp : public FpOp
        setVfpMicroFlags(mode, flags);
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 }
--- a/src/arch/arm/isa/formats/breakpoint.isa
+++ b/src/arch/arm/isa/formats/breakpoint.isa
@@ -63,10 +63,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -50,7 +50,8 @@ def template BasicDeclare {{
          public:
                /// Constructor.
                %(class_name)s(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
        };
 }};

--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, int32_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -72,8 +72,9 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, int32_t _imm,
                       ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        ArmISA::PCState branchTarget(
+                const ArmISA::PCState &branchPC) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;
@@ -105,7 +106,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -135,7 +136,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                       ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -167,7 +168,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -178,9 +179,10 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
 };
 }};

@@ -209,8 +211,9 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       int32_t imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        ArmISA::PCState branchTarget(
+                const ArmISA::PCState &branchPC) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, int64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, int64_t _imm,
                       ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       int64_t imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
                       IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2,
                int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2,
                ArmExtendType _extendType, int32_t _shiftAmt);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                       uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                       IntRegIndex _op2, ConditionCode _condCode,
                       uint8_t _defCc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _op1, IntRegIndex _op2,
                       ConditionCode _condCode);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -53,9 +53,10 @@ def template MicroMemDeclare {{
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb, bool _up,
                       uint8_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -85,9 +86,10 @@ def template MicroMemPairDeclare {{
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
                       bool _up, uint8_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -134,9 +136,10 @@ def template MicroNeonMemDeclare {{
            }
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -154,7 +157,7 @@ def template MicroSetPCCPSRDeclare {{
                       IntRegIndex _ura,
                       IntRegIndex _urb,
                       IntRegIndex _urc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -189,7 +192,7 @@ def template MicroIntDeclare {{
      public:
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb, RegIndex _urc);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -251,7 +254,7 @@ def template MicroNeonMixDeclare {{
            }
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -304,7 +307,7 @@ def template MicroNeonMixLaneDeclare {{
            }
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -319,7 +322,7 @@ def template MicroIntMovDeclare {{
      public:
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};
 def template MicroIntMovConstructor {{
@@ -350,7 +353,7 @@ def template MicroIntImmDeclare {{
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb,
                       int32_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -390,7 +393,7 @@ def template MicroIntRegDeclare {{
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb, RegIndex _urc,
                       int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -412,7 +415,7 @@ def template MicroIntXERegDeclare {{
        %(class_name)s(ExtMachInst machInst,
                       RegIndex _ura, RegIndex _urb, RegIndex _urc,
                       ArmExtendType _type, uint32_t _shiftAmt);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -582,9 +582,10 @@ def template RfeDeclare {{
        %(class_name)s(ExtMachInst machInst,
                uint32_t _base, int _mode, bool _wb);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -600,9 +601,10 @@ def template SrsDeclare {{
        %(class_name)s(ExtMachInst machInst,
                uint32_t _regMode, int _mode, bool _wb);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -618,9 +620,10 @@ def template SwapDeclare {{
        %(class_name)s(ExtMachInst machInst,
                uint32_t _dest, uint32_t _op1, uint32_t _base);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -637,9 +640,10 @@ def template LoadStoreDImmDeclare {{
                uint32_t _dest, uint32_t _dest2,
                uint32_t _base, bool _add, int32_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -656,9 +660,10 @@ def template StoreExDImmDeclare {{
                uint32_t _result, uint32_t _dest, uint32_t _dest2,
                uint32_t _base, bool _add, int32_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -674,12 +679,14 @@ def template LoadStoreImmDeclare {{
        %(class_name)s(ExtMachInst machInst,
                uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -698,9 +705,10 @@ def template StoreExImmDeclare {{
                uint32_t _result, uint32_t _dest, uint32_t _base,
                bool _add, int32_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -719,9 +727,10 @@ def template StoreDRegDeclare {{
                int32_t _shiftAmt, uint32_t _shiftType,
                uint32_t _index);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -739,12 +748,14 @@ def template StoreRegDeclare {{
                int32_t _shiftAmt, uint32_t _shiftType,
                uint32_t _index);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -765,9 +776,10 @@ def template LoadDRegDeclare {{
                int32_t _shiftAmt, uint32_t _shiftType,
                uint32_t _index);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -785,12 +797,14 @@ def template LoadRegDeclare {{
                int32_t _shiftAmt, uint32_t _shiftType,
                uint32_t _index);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -808,12 +822,14 @@ def template LoadImmDeclare {{
        %(class_name)s(ExtMachInst machInst,
                uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -259,12 +259,14 @@ def template DCStore64Declare {{
        %(class_name)s(ExtMachInst machInst, IntRegIndex _base,
                       MiscRegIndex _dest, uint64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -342,12 +344,14 @@ def template LoadStoreImm64Declare {{
        %(class_name)s(ExtMachInst machInst,
                IntRegIndex _dest, IntRegIndex _base, int64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -364,12 +368,14 @@ def template LoadStoreImmU64Declare {{
                bool noAlloc = false, bool exclusive = false,
                bool acrel = false);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -386,12 +392,14 @@ def template LoadStoreImmDU64Declare {{
                int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
                bool acrel = false);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -410,9 +418,10 @@ def template StoreImmDEx64Declare {{
                IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
                IntRegIndex _base, int64_t _imm = 0);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -427,12 +436,14 @@ def template LoadStoreReg64Declare {{
                IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
                ArmExtendType _type, uint32_t _shiftAmt);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -450,12 +461,14 @@ def template LoadStoreRegU64Declare {{
                bool noAlloc = false, bool exclusive = false,
                bool acrel = false);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -470,12 +483,14 @@ def template LoadStoreRaw64Declare {{
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _base);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -490,12 +505,14 @@ def template LoadStoreEx64Declare {{
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       IntRegIndex _base, IntRegIndex _result);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -509,12 +526,14 @@ def template LoadStoreLit64Declare {{
        /// Constructor.
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
@@ -530,12 +549,14 @@ def template LoadStoreLitU64Declare {{
                bool noAlloc = false, bool exclusive = false,
                bool acrel = false);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;

-        virtual void
-        annotateFault(ArmFault *fault) {
+        void
+        annotateFault(ArmFault *fault) override
+        {
            %(fa_code)s
        }
    };
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                       uint8_t _sysM, bool _r);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
                       uint8_t _sysM, bool _r);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
                       IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
                       MiscRegIndex _dest, uint32_t imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                       uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       IntRegIndex _op2, IntRegIndex _op3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       MiscRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, MiscRegIndex _op1,
                       uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
                       int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -623,9 +623,10 @@ def template MiscRegRegImmMemOpDeclare {{
      %(class_name)s(ExtMachInst machInst,
                     MiscRegIndex _dest, IntRegIndex _op1,
                     uint64_t _imm);
-      Fault execute(ExecContext *, Trace::InstRecord *) const;
-      Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-      Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+      Fault execute(ExecContext *, Trace::InstRecord *) const override;
+      Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+      Fault completeAcc(PacketPtr, ExecContext *,
+                        Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst,uint64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -66,7 +66,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm1, uint64_t _imm2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       IntRegIndex _op2, uint64_t _imm);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -117,7 +117,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
                IntRegIndex _op1, uint64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                MiscRegIndex _op1, uint64_t _imm);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
                       IntRegIndex _reg1, IntRegIndex _reg2);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _reg0, IntRegIndex _reg1,
                       IntRegIndex _reg2, IntRegIndex _reg3);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s
        }
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s
        }
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s
        }
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s
        }
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s
        }
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s
        %(constructor)s;
    }

-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -267,9 +267,10 @@ def template MicroNeonMemDeclare64 {{
            %(constructor)s;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

@@ -477,7 +478,7 @@ def template MicroNeonMixDeclare64 {{
            %(constructor)s;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

@@ -496,7 +497,7 @@ def template MicroNeonMixLaneDeclare64 {{
            %(constructor)s;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2,
                int32_t _shiftAmt, ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
                IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
                ArmShiftType _shiftType);
-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
    // Constructor
    %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
            uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1,
                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                  ConditionCode _cond,
                   VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s
    %(class_name)s(ExtMachInst machInst,
                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                   IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -55,11 +55,12 @@ output header {{
        /// dependence tag number (FP or int).
        void printReg(std::ostream &os, RegId reg) const;

-        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;

      public:
        void
-        advancePC(MipsISA::PCState &pc) const
+        advancePC(MipsISA::PCState &pc) const override
        {
            pc.advance();
        }
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -41,7 +41,8 @@ def template BasicDeclare {{
          public:
                /// Constructor.
                %(class_name)s(MachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
        };
 }};

--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -89,13 +89,14 @@ output header {{
            }
        }

-        MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
+        MipsISA::PCState branchTarget(
+                const MipsISA::PCState &branchPC) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -119,13 +120,13 @@ output header {{
        {
        }

-        MipsISA::PCState branchTarget(ThreadContext *tc) const;
+        MipsISA::PCState branchTarget(ThreadContext *tc) const override;

        /// Explicitly import the otherwise hidden branchTarget
        using StaticInst::branchTarget;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -47,7 +47,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };
        class CP0TLB : public MipsStaticInst
        {
@@ -59,7 +60,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };


@@ -73,7 +75,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

 }};
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -46,8 +46,6 @@ output header {{
                {
                }

-            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
                //needs function to check for fpEnable or not
        };

@@ -58,8 +56,8 @@ output header {{
                {
                }

-            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
+            std::string generateDisassembly(
+                    Addr pc, const SymbolTable *symtab) const override;
        };
 }};

--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -48,7 +48,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };


@@ -62,7 +63,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

        class HiLoRsSelOp: public HiLoOp
@@ -75,7 +77,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

        class HiLoRdSelOp: public HiLoOp
@@ -88,7 +91,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

        class HiLoRdSelValOp: public HiLoOp
@@ -101,7 +105,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

        class IntImmOp : public MipsStaticInst
@@ -124,9 +129,8 @@ output header {{
                    }
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
-
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

 }};
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -54,8 +54,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

     /**
@@ -71,8 +71,8 @@ output header {{
        {
        }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

@@ -142,9 +142,10 @@ def template LoadStoreDeclare {{
        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(Packet *, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -47,7 +47,8 @@ output header {{
                {
                }

-               std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+               std::string generateDisassembly(
+                       Addr pc, const SymbolTable *symtab) const override;

                bool user_mode;
        };
@@ -62,8 +63,6 @@ output header {{
                {
                    user_mode = true;
                }
-
-            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
        };
 }};

--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -53,10 +53,10 @@ output header {{

        ~Nop() { }

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -46,7 +46,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };
 }};

--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -47,7 +47,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };
        class TrapImm : public MipsStaticInst
        {
@@ -61,9 +62,8 @@ output header {{
                {
                }

-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
-
+                std::string generateDisassembly(
+                        Addr pc, const SymbolTable *symtab) const override;
        };

 }};
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -53,10 +53,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
    class CP0Unimplemented : public MipsStaticInst
    {
@@ -70,10 +70,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
    class CP1Unimplemented : public MipsStaticInst
    {
@@ -87,10 +87,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
    class CP2Unimplemented : public MipsStaticInst
    {
@@ -104,10 +104,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -135,10 +135,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -51,10 +51,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -86,12 +86,13 @@ class BranchPCRel : public PCDependentDisassembly
        }
    }

-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -115,12 +116,13 @@ class BranchNonPCRel : public PCDependentDisassembly
        }
    }

-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -193,12 +195,13 @@ class BranchPCRelCond : public BranchCond
        }
    }

-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -222,12 +225,13 @@ class BranchNonPCRelCond : public BranchCond
        }
    }

-    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
+    PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -243,12 +247,13 @@ class BranchRegCond : public BranchCond
    {
    }

-    PowerISA::PCState branchTarget(ThreadContext *tc) const;
+    PowerISA::PCState branchTarget(ThreadContext *tc) const override;

    /// Explicitly import the otherwise hidden branchTarget
    using StaticInst::branchTarget;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -57,7 +57,8 @@ class CondLogicOp : public PowerStaticInst
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -78,7 +79,8 @@ class CondMoveOp : public PowerStaticInst
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -145,7 +145,8 @@ class FloatOp : public PowerStaticInst
        return c;
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -91,7 +91,8 @@ class IntOp : public PowerStaticInst
        return c;
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };


@@ -113,7 +114,8 @@ class IntImmOp : public IntOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };


@@ -133,7 +135,8 @@ class IntShiftOp : public IntOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };


@@ -168,7 +171,8 @@ class IntRotateOp : public IntShiftOp
        return (rs << n) | (rs >> (32 - n));
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -53,7 +53,8 @@ class MemOp : public PowerStaticInst
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };


@@ -72,7 +73,8 @@ class MemDispOp : public MemOp
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -49,7 +49,8 @@ class MiscOp : public PowerStaticInst
    {
    }

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 } // namespace PowerISA
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -61,11 +61,11 @@ class PowerStaticInst : public StaticInst
    void
    printReg(std::ostream &os, RegId reg) const;

-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

    void
-    advancePC(PowerISA::PCState &pcState) const
+    advancePC(PowerISA::PCState &pcState) const override
    {
        pcState.advance();
    }
--- a/src/arch/power/isa/formats/basic.isa
+++ b/src/arch/power/isa/formats/basic.isa
@@ -38,7 +38,8 @@ def template BasicDeclare {{
          public:
                /// Constructor.
                %(class_name)s(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
        };
 }};

--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -44,9 +44,10 @@ def template LoadStoreDeclare {{
        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
-        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-        Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
    };
 }};

--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -55,10 +55,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };

    /**
@@ -86,10 +86,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -53,10 +53,10 @@ output header {{
            flags[IsNonSpeculative] = true;
        }

-        Fault execute(ExecContext *, Trace::InstRecord *) const;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;

-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        std::string generateDisassembly(
+                Addr pc, const SymbolTable *symtab) const override;
    };
 }};

--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -51,11 +51,8 @@ class RiscvStaticInst : public StaticInst
  protected:
    using StaticInst::StaticInst;

-    virtual std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
-
  public:
-    void advancePC(PCState &pc) const { pc.advance(); }
+    void advancePC(PCState &pc) const override { pc.advance(); }

    size_t
    asBytes(void *buf, size_t size) override
@@ -120,7 +117,7 @@ class RiscvMicroInst : public RiscvStaticInst
        flags[IsMicroop] = true;
    }

-    void advancePC(PCState &pcState) const;
+    void advancePC(PCState &pcState) const override;
 };

 }
--- a/src/arch/sparc/insts/nop.cc
+++ b/src/arch/sparc/insts/nop.cc
@@ -57,7 +57,7 @@ output header {{
            }

            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
+                    const SymbolTable *symtab) const override;
        };
 }};

--- a/src/arch/sparc/insts/priv.hh
+++ b/src/arch/sparc/insts/priv.hh
@@ -46,7 +46,8 @@ class Priv : public SparcStaticInst
 {
  protected:
    using SparcStaticInst::SparcStaticInst;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 class PrivReg : public Priv
@@ -66,7 +67,8 @@ class RdPriv : public PrivReg
 {
  protected:
    using PrivReg::PrivReg;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 // This class is for instructions that explicitly write control
@@ -75,7 +77,8 @@ class WrPriv : public PrivReg
 {
  protected:
    using PrivReg::PrivReg;
-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;
 };

 /**
@@ -103,11 +106,12 @@ class WrPrivImm : public PrivImm
        PrivImm(mnem, _machInst, __opClass), regName(_regName)
    {}

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

    char const *regName;
-}
-;
+};
+
 }

 #endif //__ARCH_SPARC_INSTS_PRIV_HH__
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -90,7 +90,8 @@ class SparcStaticInst : public StaticInst
  protected:
    using StaticInst::StaticInst;

-    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    std::string generateDisassembly(
+            Addr pc, const SymbolTable *symtab) const override;

    static void printMnemonic(std::ostream &os, const char *mnemonic);
    static void printReg(std::ostream &os, RegId reg);
@@ -101,7 +102,7 @@ class SparcStaticInst : public StaticInst
    void printRegArray(std::ostream &os,
        const RegId indexArray[], int num) const;

-    void advancePC(PCState &pcState) const;
+    void advancePC(PCState &pcState) const override;

    static bool passesFpCondition(uint32_t fcc, uint32_t condition);
    static bool passesCondition(uint32_t codes, uint32_t condition);
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -38,7 +38,7 @@ class %(class_name)s : public %(base_class)s
  public:
    // Constructor.
    %(class_name)s(ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

@@ -52,7 +52,7 @@ class %(class_name)s : public %(base_class)s
  public:
    // Constructor.
    %(class_name)s(ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
    Fault doFpOp(ExecContext *, Trace::InstRecord *) const M5_NO_INLINE;
 };
 }};
@@ -67,7 +67,7 @@ class %(class_name)s : public %(base_class)s
  public:
    // Constructor.
    %(class_name)s(const char *mnemonic, ExtMachInst machInst);
-    Fault execute(ExecContext *, Trace::InstRecord *) const;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
 };
 }};

--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -45,10 +45,11 @@ def template MemDeclare {{
            /// Constructor.
            %(class_name)s(ExtMachInst machInst);

-            Fault execute(ExecContext *, Trace::InstRecord *) const;
-            Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+            Fault execute(ExecContext *, Trace::InstRecord *) const override;
+            Fault initiateAcc(ExecContext *,
+                              Trace::InstRecord *) const override;
            Fault completeAcc(PacketPtr, ExecContext *,
-                              Trace::InstRecord *) const;
+                              Trace::InstRecord *) const override;
        };
 }};

--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -48,10 +48,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_0(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_1 : public %(base_class)sMicro
@@ -59,10 +61,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_1(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_2 : public %(base_class)sMicro
@@ -70,10 +74,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_2(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_3 : public %(base_class)sMicro
@@ -81,10 +87,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_3(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_4 : public %(base_class)sMicro
@@ -92,10 +100,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_4(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_5 : public %(base_class)sMicro
@@ -103,10 +113,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_5(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_6 : public %(base_class)sMicro
@@ -114,10 +126,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_6(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };

            class %(class_name)s_7 : public %(base_class)sMicro
@@ -125,10 +139,12 @@ def template BlockMemDeclare {{
              public:
                // Constructor
                %(class_name)s_7(ExtMachInst machInst);
-                Fault execute(ExecContext *, Trace::InstRecord *) const;
-                Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+                Fault execute(ExecContext *,
+                              Trace::InstRecord *) const override;
+                Fault initiateAcc(ExecContext *,
+                                  Trace::InstRecord *) const override;
                Fault completeAcc(PacketPtr, ExecContext *,
-                                  Trace::InstRecord *) const;
+                                  Trace::InstRecord *) const override;
            };
        };
 }};