Yifei Liu d3a87a87b4 arch-riscv: Update register file ...

This patch adds mcounteren, scounteren according to Risc-V
Privileged Architectures V1.10.

Change-Id: I6e138a50710bc0a1e9d9c38a11fc7fcc09ed500e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20128
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2019-08-21 17:52:54 +00:00

..

arch

arch-riscv: Update register file

2019-08-21 17:52:54 +00:00

base

base: assert that stats bucket size is greater than 0

2019-08-21 12:16:48 +00:00

cpu

arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

2019-08-21 12:17:17 +00:00

dev

dev-arm: Add redistributor-stride property to GICv3

2019-08-20 14:23:47 +00:00

doc

mem: Minimize the use of MemObject.

2019-04-28 01:19:40 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.

2019-05-30 14:20:03 +00:00

kern

kern: Replace an explicitly instantiated port proxy with one from the tc.

2019-05-30 14:20:03 +00:00

learning_gem5

learning_gem5: Fix vector port panic in SimpleCache

2019-04-08 22:51:38 +00:00

mem

mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer

2019-08-19 17:00:33 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: FdtState using interrupt-cells

2019-08-12 18:17:45 +00:00

sim

sim: Add a hook Clocked objects can implement for frequency changes.

2019-08-13 22:32:31 +00:00

systemc

systemc: Provide Port wrapper classes for sc_port

2019-08-05 03:19:36 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Move the marshal binary to the build directory

2019-05-21 15:46:50 +00:00