3783cc0de0
The runtime coherence check should check the cache heirarchy, not the global protocol so it can differentiate between Ruby and classic. This patch also removes some unnecessary includes and fails earlier in MESI_Two_Level if that protocol isn't built. Change-Id: I31c1fbd1d9597163b9138e80619d05c132a91545 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49345 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
90 lines
3.7 KiB
Python
90 lines
3.7 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from components_library.utils.override import overrides
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from components_library.boards.mem_mode import MemMode
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from components_library.processors.simple_core import SimpleCore
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from m5.util import warn
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from .abstract_processor import AbstractProcessor
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from .cpu_types import CPUTypes
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from ..boards.abstract_board import AbstractBoard
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from typing import List
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class SimpleProcessor(AbstractProcessor):
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"""
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A SimpeProcessor contains a number of cores of a a single CPUType.
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"""
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def __init__(self, cpu_type: CPUTypes, num_cores: int) -> None:
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super(SimpleProcessor, self).__init__(
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cores=self._create_cores(
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cpu_type=cpu_type,
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num_cores=num_cores,
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)
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)
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self._cpu_type = cpu_type
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if self._cpu_type == CPUTypes.KVM:
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self.kvm_vm = KvmVM()
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# To get the KVM CPUs to run on different host CPUs
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# Specify a different event queue for each CPU
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for i, core in enumerate(self.cores):
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for obj in core.get_simobject().descendants():
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obj.eventq_index = 0
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core.get_simobject().eventq_index = i + 1
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def _create_cores(self, cpu_type: CPUTypes, num_cores: int):
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return [
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SimpleCore(cpu_type=cpu_type, core_id=i) for i in range(num_cores)
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]
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@overrides(AbstractProcessor)
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def incorporate_processor(self, board: AbstractBoard) -> None:
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if self._cpu_type == CPUTypes.KVM:
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board.kvm_vm = self.kvm_vm
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# Set the memory mode.
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if self._cpu_type == CPUTypes.TIMING or self._cpu_type == CPUTypes.O3:
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board.set_mem_mode(MemMode.TIMING)
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elif self._cpu_type == CPUTypes.KVM:
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board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
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elif self._cpu_type == CPUTypes.ATOMIC:
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if board.get_cache_hierarchy().is_ruby():
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warn(
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"Using an atomic core with Ruby will result in "
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"'atomic_noncaching' memory mode. This will skip caching "
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"completely."
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)
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else:
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board.set_mem_mode(MemMode.ATOMIC)
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else:
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raise NotImplementedError
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